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Product category: Design and Development Software
News Release from: Mentor Graphics UK | Subject: FormalPro
Edited by the Electronicstalk Editorial Team on 16 July 2001

Equivalence checker goes multilingual

Mentor Graphics has released an enhanced version of its FormalPro formal verification tool aimed at multi-million-gate ASIC and SoC designs

The enhancement allows designers to perform equivalence checking on designs containing mixed-HDL throughout the hierarchy. "We see an increasing number of designs that contain both Verilog and VHDL, and a corresponding increase in demand for a formal verification solution that provides seamless support for both languages throughout the design flow", said Reily Jacoby, FormalPro product line manager at Mentor Graphics.

"By using technology from the ModelSim simulator, we provide a solution that has already been tested and proven in literally tens of thousands of designs".

FormalPro has been extended to allow fully mixed HDL designs to be formally verified with any mix of VHDL and Verilog at the RTL and/or gate level.

The tool supports multiple levels of VHDL instantiating Verilog, and Verilog instantiating VHDL.

Passing of parameters and generics is handled automatically throughout the design hierarchies, making reuse and verification of generic HDL models very simple.

The trend toward increased use of mixed-language design is a result of many factors.

Today, many designs incorporate both internal and external IP.

Also, as a result of globalisation and acquisitions, designs are often developed in different parts of the world, using different languages.

Finally, as SoC designs become more and more common, the integration of chipsets with heterogeneous HDLs into one chip is rapidly increasing.

The FormalPro approach to equivalence checking enables designers to formally verify designs with over 20 million gates in a matter of hours on a standard 32bit workstation.

FormalPro's high capacity means it does not have to rely on hierarchical partitioning, which enables multi-million-gate flat netlists to be automatically compared with hierarchical RTL.

Hierarchical verification methods often require lengthy setup times, while reporting more false differences that require analysis by the designer.

With FormalPro, designers can execute multiple daily runs of large designs without having to partition an SoC or ASIC design into blocks.

This increases productivity and decreases the risk of errors split across blocks.

The tool's minimal setup requirements save designers time and allows the easy adoption of formal verification technology into any design flow.

Multiple matching techniques, coupled with multiple solver technology, ensure an automated flow.

FormalPro's advanced debugging technology quickly performs automated analysis of failing comparison points, isolates the exact location of the error and allows the designer to try out different possible corrections on-the-fly, increasing a design team's productivity and shortening turnaround times.

The enhanced version of FormalPro is currently in beta testing.

It will be available in Q4 2001 at no additional fee to current FormalPro customers.

FormalPro pricing starts at $110,000.

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