Product category: Design and Development Software
News Release from: Magma Design Automation | Subject: Talus
Edited by the Electronicstalk Editorial Team on 24 April 2006
EDA tools claim true
automation of IC design
An all-new IC implementation product line that offers unequalled automation and virtually unlimited capacity while delivering improved timing, area, power, signal integrity and manufacturability
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Magma Design Automation has unveiled Talus, an all-new integrated circuit (IC) implementation product line that offers unequalled automation and virtually unlimited capacity while delivering improved timing, area, power, signal integrity and manufacturability. With Talus, Magma fulfils the promise of electronic design automation (EDA), rather than providing mere electronic design assistance, as traditional tools have.
The advanced implementation capabilities in Talus are designed to dramatically reduce the design development cycle and design costs, and speed yield ramp-up for ICs targeted at 65nm and smaller process geometries.
'Talus delivers what EDA has long promised', said Rajeev Madhavan, CEO of Magma.
'At each process node, development costs are increasing and profits per design are decreasing'.
'To reverse that trend, IC vendors need true design automation so they can accelerate the design cycle and maximise their engineering resources - that's what Talus delivers'.
Talus provides a complete RTL-to-tape-out platform that concurrently analyses and optimises timing, area, power, signal integrity and yield.
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It enables Automated Chip Creation, a new methodology for IC implementation that drastically improves engineering productivity.
With Talus, floorplanning has been transformed into an automated physical synthesis process.
Leveraging a new constraint set called Relative Placement Constraints, Talus eliminates the need for the traditionally labour-intensive and time-consuming floorplanning and prototyping tasks.
Design for variability on complex designs is supported through concurrent multimode/multicorner and native on-chip variation (OCV) analysis with timing and crosstalk noise optimisations.
Talus' advanced timing capabilities eliminate the need for iterative analysis and optimisation runs to meet multiple mode and corner constraints.
Talus also incorporates sophisticated routing algorithms developed in conjunction with IBM and the University of Bonn.
Talus is the first system in which the entire implementation flow is lithography-aware.
This unique capability minimises the key source of deterministic variability in 65 and 45nm designs.
Talus' Automated Chip Creation methodology enables designers to create either preliminary or final-quality layouts, physically flat or hierarchically, in just a few hours and for any size design.
The process can begin with as little as 10% of the design RTL available.
With fast and accurate feedback early in the cycle, users can identify the top-level timing constraints that meet block timing budgets, enabling them to avoid timing violations later during chip integration.
With each subsequent RTL change, Talus automatically creates multiple floorplans, allowing designers to see in real-time the impact of those changes on chip size.
Predictability for subsequent trials is managed with the Relative Placement Constraints, which enable the user to reproduce desired aspects of a previous floorplan.
This unprecedented level of automation expands the user's efficiency at all stages of design development.
Early in the process, fast implementation trials can be conducted to establish accurate timing constraints, investigate floorplan alternatives, and trade off package decisions with respect to design speed, area, noise, yield and power integrity.
Late in the process, the schedule impact of late-arriving RTL and design requirement changes is minimised because the required production floorplan changes are handled automatically.
To further accelerate the design cycle and provide the highest capacity, Talus leverages multithreading and distributed processing, allowing users to implement very large designs in just two days.
With faster design cycles, higher capacity and the ability to automatically and effectively address all design objectives, Talus users will be able to devote more time to product innovation, reduce IC development costs and increase yields.
A number of full-chip designs targeted for various applications and ranging in size from 4 to 15 million gates have been taken through the Talus flow.
Results have demonstrated productivity improvements and significant area savings over conventional design techniques.
'Hierarchical design demands a significant amount of time and number of resources, especially when the RTL code is changing', said John Fallin, Executive Director, Custom SoC Engineering, NEC Electronics America.
'By using Talus, we will have a viable flat design methodology for 12-million-gate and larger chips that is able to confirm new floorplans overnight, quickly validate chip-level timing constraints, and give us confidence that the design is production worthy'.
The Talus LX and Talus PX products provide the foundation of the Automated Chip Creation methodology for logic and physical design engineers.
Both are built on Magma's unified data model architecture offering a tightly integrated IC implementation flow.
Talus LX synthesises chip RTL for given timing, power and placement constraints and automatically generates physical partitions and power and clock prototypes.
This automated solution empowers logic designers to rapidly explore the design space and implement the most optimal solution without detailed knowledge of physical design and without sacrificing the schedule, or quality of the design.
Talus PX provides complete physical implementation of the design including near abutment layout, final physical partitions, power and signal routing, and chip-level clock tree synthesis.
This integrated physical design environment delivers improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows.
Both products are currently in limited release.
Pricing will be available with the production release scheduled for 2006.
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