Product category: Intellectual Property Cores
News Release from: LSI Europe | Subject: ECC memory protection core
Edited by the Electronicstalk Editorial Team on 20 October 2004
Novel ECC core cuts
errors in ARM-based SoCs
A new ECC memory protection core is billed as a significant development in addressing soft error rates in ARM core based SoC designs
This week at the ARM Developers Conference LSI Logic Corp revealed a significant development in addressing soft error rates (SERs) in ARM core based SoC designs with the introduction of an error checking and correction (ECC) core. Soft errors, which are caused by radiation, are an industry-wide problem that is becoming more severe with shrinking geometries.
This article was originally published on Electronicstalk on 20 October 2004 at 8.00am (UK)
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In many applications, especially storage and networking, error correction and detection codes are becoming a firm requirement to achieve acceptable mean-time-between-failure rates.
The ECC memory protection core, the newest addition to LSI Logic's CoreWare intellectual property (IP) library, minimises die area without sacrificing performance.
The LSI Logic ECC core provides SECDED (single error correct double error detect) protection for the tightly coupled memories (TCMs) of the ARM9 and ARM11 family of processors, and is the first in the industry to use a word-based 7bit ECC code instead of a commonly used byte-based 20bit ECC code with a processor tightly coupled memory.
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By adding a write buffer and read-modify-write circuitry along with innovative control circuitry, the LSI Logic ECC core provides negligible performance impact while allowing for the reduction in check bits, resulting in significant die area and total system cost savings as compared with standard ECC and parity solutions.
For example, 5mm2 of die area savings can be realised using the LSI Logic ECC core in a 0.11 micron ARM966 application with 128Kbyte instruction and 128Kbyte data TCMs using high-density memories.
"We designed the ECC core with performance in mind", said Harmel Sangha, Director of CoreWare Marketing and Customer Support, LSI Logic.
"By taking the ECC core all the way through layout with a real ARM processor, we identified the critical paths and modified the RTL accordingly to provide maximum processor performance".
"As an example, the ECC core will run at 240MHs with an ARM966E-S core with 64Kbyte TCMs in our 0.11-micron technology".
Additionally, the use of a very intelligent write buffer in the LSI Logic ECC core eliminates virtually all stall cycles for further processor performance.
In a traditional read-modify-write implementation, a byte write to the TCM causes a cycle of latency.
The intelligent write buffer in the LSI Logic ECC core design takes advantage of cycles where the memory is not being accessed to prevent stalls in all but the most extreme corner cases.
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