Product category: Design and Development Software
News Release from: LSI Europe | Subject: RapidWorx
Edited by the Electronicstalk Editorial Team on 25 June 2003
Dedicated design system
speeds RapidChip ASICs
RapidWorx is an innovative design system for LSI Logic RapidChip platform ASIC products
RapidWorx significantly reduces design obstacles for high-performance, custom silicon, making the design of RapidChip products fast, predictable and affordable for a broader range of markets. RapidWorx achieves this through the combination of a streamlined design flow, rule-based methodology and automated, correct-by-construction tools.
This article was originally published on Electronicstalk on 25 June 2003 at 8.00am (UK)
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Using RapidWorx, customers quickly achieve design handoff that allows LSI Logic to tape-out to manufacturing as fast as one million gates per week.
"LSI Logic is delivering RapidWorx to bring, for the first time, high complexity chip design to the masses", said Ronnie Vasishta, Vice President, Technology Marketing and CoreWare Engineering, LSI Logic Corp.
"LSI Logic's customer focus demands that we deliver end-to-end solutions.
RapidChip dramatically reduces the time to design with silicon platforms, a rich library of IP, and tools and methodology optimised for the platform".
The RapidWorx streamlined design flow consists of five basic steps: configuration of the RapidChip slice resources, physical mapping of those resources, RTL rule checking with physical RTL analysis, physical synthesis, and netlist handoff rule checking.
Each step is executed by a tool launched within the RapidWorx cockpit.
The tools are tightly integrated, enabling features such as crossprobing between tools.
RapidWorx is a rule-based design system that ensures first-pass success.
RTL rule compliance is done early in the design cycle, preventing RTL problems that can only be fixed with changes in RTL code or synthesis strategy from propagating further into the design flow.
The final gate-level netlist check prior to handoff ensures the one million gates per week layout cycle.
The RapidWorx design system avoids user and implementation errors with automated, correct-by-construction tools.
Iterations between logical and physical design are avoided because design integrity and other physical issues are addressed automatically in the tools.
Many design integrity issues are addressed in the pre-built RapidChip slices, removing them from the design flow completely.
RapidWorx customer engagements will start July 2003.
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