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Product category: Design and Development Software
News Release from: LSI Europe | Subject: PRO
Edited by the Electronicstalk Editorial Team on 19 November 2002

RTL optimisation spots SoC bugs earlier

LSI Logic has developed a novel physical RTL optimisation (PRO) flow to identify physical design issues early in complex SoC design cycles

LSI Logic is first in the industry to directly link routing and congestion problems in physical design back to the RTL code, while the code is still being developed, allowing engineers to quickly and predictably resolve major physical design issues at the RTL stage. By minimising the number of iterations between logical and physical design, the LSI Logic PRO flow allows engineers to be confident in achieving predictable design closure and meeting crucial time-to-market windows.

"Our customers require increasingly complex, high-performance, high-density designs in right-first-time, on time silicon, and our ability to provide quick feedback is immensely helpful to design engineers", said Jeff Vanderlip, director, ASIC Technical Marketing, LSI Logic Corporation.

"With physical RTL optimisation, we analyse, identify and resolve RTL architecture and coding issues that cause layout bottlenecks, while the RTL code is being written.

This provides substantial improvement in layout predictability and turnaround time".

In complex SoC designs, major physical design issues must be resolved in either the chip-level architecture or the RTL architecture and coding.

Once RTL is coded, resolving major physical design issues often requires time-consuming iterations.

The LSI Logic PRO flow provides a pre-emptive diagnosis on the RTL code, allowing early visibility into issues such as routing congestion and critical path timing violations created by suboptimal RTL coding and architecture.

"Current-generation tools and flows focus on optimisation at the gate-level", said Juergen Lahner, manager of LSI Logic's RTL Handover group.

"The majority of physical design problems are inherent in RTL coding and architecture and they are not identifiable once the RTL has been synthesised into a gate-level netlist.

Without directly linking timing and congestion problems in physical design to the source of the problem in RTL code, designers are subjected to resolving physical RTL problems through a difficult and lengthy iterative process".

LSI Logic targets physical RTL optimisation on all of its Gflx 0.11-micron and G90 90nm designs, as well as the majority of its G12 0.18-micron designs.

Expanding the current access of the PRO flow by LSI Logic ASIC customer engineers in the company's design centres worldwide, the LSI Logic PRO flow is now available for use at customer sites.

By having the LSI Logic PRO flow readily accessible, customers can be relieved of RTL code confidentiality concerns, and they realise faster design iterations by shortening the learning curve for developing physically optimised RTL code.

Customers choosing on-site access will retain full support of LSI Logic ASIC customer engineers who will analyse LSI Logic PRO results and identify major problems in customer design codes within a few days of receiving a report.

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