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Product category: Electronics Manufacturing Machinery and Materials
News Release from: LSI Europe | Subject: Pad on I/O
Edited by the Electronicstalk Editorial Team on 24 October 2002

I/O scheme makes the most
of 90nm ASIC wire bonds

Pad on I/O is an industry first for copper/low-K processes in wire bond packaging

The LSI Logic Pad on I/O technology places bond pads directly on top of active I/O circuits in a chip design. Pad on I/O was developed for the LSI Logic Gflx (0.11um) and G90 (90nm) silicon technologies. The Pad on I/O technology provides ASIC/SoC/RapidChip platform designers with the industry's most cost-effective chip design by reducing die area up to 50% when compared with standard wire bond designs.

The company designed robust bond pad structures and metal stack-up schemes to ensure that the mechanical integrity of the silicon chip is not compromised.

The enhanced silicon design features allow LSI Logic to use industry-standard wire bond equipment, resulting in cost effective high-volume assembly.

"LSI Logic's Pad on I/O technology, especially for high performance copper die, has the potential to significantly extend the use of low cost wire bonding over flip chip", said Neil Moskowitz, senior analyst at Prismark Partners.

"Increasing interconnect density, power and ground access to die centre, and increasing silicon utilisation are some of the potential benefits of this technology".

"LSI Logic created an innovative packaging technology that allows system-on-a-chip designers to take full advantage of geometry shrinks in Gflx and G90.

The result is a chip design that maximises silicon area while maintaining cost effectiveness", said Maniam Alagaratnam, vice president of package development for LSI Logic.

"Our engineering teams continue to exhibit tremendous technical prowess by developing this capability in copper/low K as well as an assembly process for reliable wire bonding on top of active circuits".

Pad on I/O can be used for inline or staggered pad designs.

For staggered pad designs, LSI Logic offers ASIC/SoC/RapidChip designers the option of designing up to three rows of staggered pads.

Pad on I/O provides a staggered pad pitch of 27mm effective when compared to the industry standard two-row staggered pad approaches.

All standard packages offered by LSI Logic have been optimised to fully utilise Pad on I/O.

"As the industry leader in system on chip solutions, LSI Logic continues to take the communications, consumer and storage markets into new areas by developing leading packaging technologies and innovations", said Stan Mihelcic, manager of Advanced Packaging Solutions, Technology Marketing, LSI Logic Corporation.

"With the advent of 110 and 90nm silicon processes, packaging is being challenged to keep up with density increases and resulting die size reductions in silicon design.

With LSI Logic's advanced silicon process technologies, Gflx and G90, Pad on I/O provides robust design solutions, resulting in the most cost competitive ASIC/SoC/RapidChip designs in the industry".

Pad on I/O is available now and is used for all wire bond designs in Gflx and G90 silicon designs.

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