Product category: Design and Development Software
News Release from: LogicVision Europe | Subject: ETCompression
Edited by the Electronicstalk Editorial Team on 24 May 2006
Compression software tests chips at-speed
New from LogicVision, ETCompression is a deterministic test compression solution targeted at chips designed at advanced nanometre scale technology nodes
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ETCompression provides the first true at-speed launch-on-shift test application using LogicVision's patent pending Burst-Mode test timing architecture. This provides both very high transition fault coverage as well as signal integrity screening through run-time control of internal scan rates and functional clock cycle spreading.
At-speed test has become a requirement for designers of today's highly integrated circuits, as semiconductor manufacturers are faced with increasingly subtle defect mechanisms and new process-design interactions, resulting in an increasing number of performance and quality issues.
ETCompression provides the unique ability to test chips at-speed, under conditions which simulate actual functional operation, and does so with substantial test time and test data volume reductions.
The result is an unmatched level of coverage and quality, at a lower test cost.
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LogicVision has appointed ISS Group to distribute its products in the UK, Norway, Poland, Finland, Ireland, Denmark and Sweden
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ETCompression builds on LogicVision's industry leading embedded logic test solutions, including a hierarchical architecture that provides both high scalability and full core reuse leading to significant integration efficiencies and time to market savings.
ETCompression can be used purely with compressed deterministic scan patterns, or be seamlessly complemented with the application of pseudorandom patterns to achieve the highest quality levels required in communication, consumer, storage and automotive devices.
Tool capabilities include: over 10x test time and 100x test data volume reduction; patent pending Burst-Mode test timing architecture for true at-speed test application and run-time programmable power management and characterisation; IEEE1500 compliant distributed test access architecture and patented core shared isolation for hierarchical test integration for minimising area overhead and performance impact; automated RT level test analysis, generation and insertion flow for fast test integration, including handling of unknowns, and automated fixing of violations; and full physical design flow integration, including automated generation of design constraints, synthesis scripts, timing analysis, formal verification and testbench generation.
'At advanced process nodes the industry needs to maintain test quality and good yields while containing test costs in order to remain competitive', said Jim Healy, President and CEO of LogicVision.
'Testing chips under functional conditions is essential to ensure ultimate product quality, and ETCompression offers this key capability, allowing users to execute a comprehensive SoC test plan efficiently while controlling costs'.
ETCompression is available immediately.
ETCompression works seamlessly with other LogicVision tools and is interoperable with all major physical design flows, including Cadence Design Systems, Magma Design Automation, and Synopsys.
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