Visit the National Instruments web site

DFT analyser reduces test and prototyping costs

A Logic Technology product story
More from this company More from this category
Edited by the Electronicstalk editorial team Nov 4, 2005

The DFT analyser from Asset InterTech reduces manufacturing and test costs by validating the boundary-scan design-for-test (DFT) features in a circuit board design before prototypes are assembled.

The DFT analyser from Asset InterTech, which specialises in boundary-scan (IEEE 1149.1/JTAG) test and in-system programming (ISP ), reduces manufacturing and test costs by validating the boundary-scan design-for-test (DFT) features in a