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Product category: Design and Development Software
News Release from: Lattice Semiconductor UK | Subject: IspLever
Edited by the Electronicstalk Editorial Team on 22 April 2008
FPGA design tools add mixed language
simulator
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Active-HDL Lattice Edition will be bundled with the next version of Lattice's ispLever design tool suite.
Lattice Semiconductor and Aldec have signed an OEM agreement that will deliver the only OEM FPGA mixed language simulator Active-HDL Lattice Edition will be bundled with Lattice's ispLever design tool suite, providing mixed language simulation (VHDL, Verilog and SystemVerilog), cosimulation with Simulink from The MathWorks and simulation support for Lattice encrypted IP cores
This article was originally published on Electronicstalk on 24 Apr 2002 at 8.00am (UK)