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Product category: Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: LatticeECP2M family'
Edited by the Electronicstalk Editorial Team on 22 September 2006

Low-cost FPGAs embed high-speed serdes
I/O

The LatticeECP2M FPGA family are the industry's first low cost FPGAs offering high-speed embedded serdes I/O plus a pre-engineered Physical Coding Sublayer block.

Lattice Semiconductor Corp has announced the LatticeECP2M FPGA family, the industry's first low cost FPGAs offering high-speed embedded serdes I/O plus a pre-engineered Physical Coding Sublayer (PCS) block Based on the innovative LatticeECP2 low cost architecture, the new LatticeECP2M family also has been developed on advanced 90nm CMOS technology using 300mm wafers

Previously, high-speed embedded serdes serial I/O with speeds over 3Gbit/s has been available only on relatively expensive high-end FPGAs.

Integrating this capability into a low cost FPGA fabric makes this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video, and industrial equipment.

Priced at approximately one-third the cost of competitive serdes-based FPGAs, the ECP2M FPGA family effectively bridges the price/performance gap between low cost and high-end FPGAs.