FPGA family takes on more system functions

The LatticeSC System Chip FPGA family is designed to provide the performance and connectivity essential for high-speed applications.

The LatticeSC System Chip FPGA family is designed to provide the performance and connectivity essential for high-speed applications.

Fabricated on Fujitsu's 90nm CMOS process technology using 300mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity to provide "extreme performance".

The LatticeSC devices are being announced by Lattice in conjunction with its second-generation low-cost LatticeECP2 family, also fabricated on the same 90nm technology.

Integrated into the LatticeSC devices are high-channel count serdes blocks supporting 3.4Gbit/s datarates, Purespeed parallel I/O providing an industry-leading 2Gbit/s speed, innovative clock management structures, FPGA logic operating at 500MHz, dense block RAM and Lattice's unique Masked Array for Cost Optimisation (MACO) embedded structured ASIC blocks.

"LatticeSC FPGAs deliver the highest performance and most robust feature set of any programmable logic product in the industry".

"Combined with our new low cost LatticeECP2 devices, and the nonvolatile MachXO and LatticeXP devices, the LatticeSC family establishes the Lattice FPGA portfolio as the broadest and deepest in the market", said Stan Kopec, Lattice Corporate Vice President of Marketing.

"LatticeSC devices are architected with high performance protocol-based connectivity in mind", Kopec added.

"The LatticeSC FPGA supports an immense breadth of protocols, including PCI Express, Serial RapidIO, Ethernet, Fibre Channel, Sonet/SDH and SPI4.2, as well as all the high performance memory standards, including DDR2, QDR2 and RLDRAM.

This level of innovation, integration, standards support and speed in an FPGA is unprecedented", Kopec concluded.

Lattice FPSCs (Field Programmable System Chips) were the first programmable logic dev