Product category: Design and Development Software
News Release from: Lattice Semiconductor UK | Subject: IspLever
Edited by the Electronicstalk Editorial Team on 01 December 2004
Tool suite boasts faster FPGA design
The latest release of the ispLever programmable logic design tool suite offers a comprehensive upgrade and enhancement in performance and functionality.
The latest release of the ispLever programmable logic design tool suite offers a comprehensive upgrade and enhancement in performance and functionality FPGA Fmax performance has been increased by an average 22% and map, place and route runtimes have been reduced by 24% for a typical design, lessening the demand on computing resources
This article was originally published on Electronicstalk on 24 Apr 2002 at 8.00am (UK)
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The simple machine for complex design
"The simple machine for complex design" is the description given by Lattice Semiconductor to its next-generation ispLever design tools.
The simple machine for complex design
Dubbed "The simple machine for complex design", the latest generation of the ispLever design tool provides developers a simple powerful tool to use with all of Lattice's programmable logic products.
Enhancements include an I/O assistant for efficient placement of mixed I/O types, the addition of new power calculator and ispTracy logic analyser tools, a new project creation wizard, major upgrades in static timing analysis, floorplanning and DSP design, and a significantly faster and more fully featured ModelSim simulator from Mentor Graphics.
The ispLever design tools support all Lattice digital programmable logic devices, including the new LatticeECP-DSP (Economy Plus DSP) and LatticeEC (Economy) FPGA device families, and provide all the features required to develop a design from concept to programmed device.
"The ispLever 4.2 sui