Product category: Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ispXPLD 51024MX and ispXPLD 5256MX
Edited by the Electronicstalk Editorial Team on 15 August 2003
In-system programmable PLD runs to 1024
macrocells
Lattice Semiconductor has added of two new devices to its revolutionary in-system programmable expanded PLD family, the ispXPLD 51024MX and ispXPLD 5256MX devices.
Lattice Semiconductor has added of two new devices to its revolutionary in-system programmable expanded PLD family, the ispXPLD 51024MX and ispXPLD 5256MX devices The ispXPLD 51024MX features up to 1024 logic macrocells and up to 512Kbit of on-chip memory and represents the largest member of the family
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
Related stories
Big, fast and wide PLDs in full production
Lattice Semiconductor has announced the completion of the production release of its second-generation SuperFAST BFW (Big-Fast-Wide) family, the ispLSI 2000VE family.
Analogue front end is dynamically reconfigurable
Lattice Semiconductor has added a new member to its ispPAC programmable analogue device family.
The ispXPLD 5256MX provides up to 256 logic macrocells and up to 128Kbit of on-chip memory and is the smallest member of the device family.
The ispXPLD architecture is the first PLD architecture that allows users to efficiently trade off fast logic and block memory resources.
The unique architecture offers multifunction blocks (MFBs) that can be independently used for logic functions (up to 32 macrocells per MFB) or memory functions (up to 16Kbit per MFB), yielding up to 1024 logic macrocells or 512Kbit of on-chip memory on a single device, equivalent to 300K system gates.