Novel PLD trades logic and memory functions

The ispXPLD (in-system programmable expanded PLD) architecture is the first PLD architecture to allows users to efficiently trade-off fast logic and block memory resources.

The ispXPLD (in-system programmable expanded PLD) architecture is the first PLD architecture to allows users to efficiently trade-off fast logic and block memory resources.

The novel architecture allows each multifunction block (MFB) to be used for logic functions (up to 32 macrocells per MFB) or memory functions (up to 16Kbit per MFB), yielding up to 1024 macrocells or 512Kbit of memory on a single device, equivalent to 300K system gates.

The SuperWide architecture also supports functions of up to 136 inputs in a single level of logic, doubling the fan-in of any other PLD family and providing fast support for extremely wide buses and logic functions.

Performance of up to 285MHz, with pin-to-pin logic delay of 3.5ns and clock-to-output delay of 2.5ns is specified.

The ispXPLD family also uses Lattice's new ispXP (ISP expanded programming) technology that combines the traditional product-term based PLD benefit of "instant-on", nonvolatile programming together with real time, unlimited reconfigurability found in SRAM-based FPGAs.

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