Product category: Design and Development Hardware
News Release from: Inovys Corp | Subject: Personal Ocelot
Edited by the Electronicstalk Editorial Team on 1 October 2003

Link puts desktop ATE into design chain

Inovys Corp has added a bidirectional link between its Personal Ocelot desktop automatic test equipment and the Cadence Encounter Test Solutions toolsuite

Inovys Corp has added a bidirectional link between its Personal Ocelot desktop automatic test equipment (ATE) and the Cadence Encounter Test Solutions toolsuite based on design chain collaboration work done through the Cadence Connections programme. This link, which is based on the IEEE1450 Standard Test Interface Language (STIL), adds design and test generation information to patterns inputs to the ATE for manufacturing test and to enable direct transfer of device-failure data from the ATE back to the Cadence fault-isolation tool for failure diagnostics.

Using this linked automatic test-pattern generation (ATPG)-ATE solution, designers can quickly pinpoint and analyse defects including speed-related delay and transition faults, enabling them to achieve rapid yield improvement of their complex ICs.

"Market demands to achieve the highest product quality and shortest time to volume at the lowest cost make quick, accurate failure diagnostics in the design for test (DFT) flow a must-have", said Dr Bernd Koenemann, a Cadence Fellow.

"Inovys' active participation in the Cadence Connections programme has resulted in links between the diagnostics capabilities of Cadence Encounter Test Solutions with Inovys' high-performance structural testers.

This enables manufacturers of complex ICs to discover and analyse both design and manufacturing defects quickly, thereby helping our customers improve their yield and profitability".

Working closely with Cadence, Inovys has verified the interoperability between the Encounter Test Solutions test-generation and fault-isolation tools and the Inovys Stylus ATE operating system.

Using IEEE STIL, the Inovys tester directly reads and executes DFT test patterns generated by Cadence without intermediate translation steps.

Included in the STIL test patterns is information that identifies each test pattern and that is echoed back in the fail log from Stylus.

This identifier directs brings the fault-isolation tool back to the exact place and time where the original pattern was generated without the need for workarounds or scripting.

The link between Inovys ATE and the Cadence Encounter Test Solutions tool suite is the basis for continuing integration work by the two companies, which is anticipated to generate additional automated analysis processes.

"Fabless semiconductor manufacturers face considerable difficulty in executing failure diagnosis if they depend on scheduling traditional, raised-floor test equipment", said Phil Burlison, Inovys Chief Technology Officer.

"As a result, despite the increasing use of scan, its enhanced failure diagnosis potential is typically underutilised, crippling the potential for faster production ramps and higher yields for complex devices.

Inovys' provision of an open STIL-based-standard ATPG-ATE interface, our capability to provide formatted failure information for Cadence's fault isolation tool, and our ability to execute the path-delay and transition-fault test patterns generated by the Encounter test software enables our customers to achieve faster manufacturing ramp-up with higher fault coverage and accelerated yield improvement for their products".

Inovys and Cadence have made significant contributions focusing on the development of the DFT-based manufacturing yield analysis, and the Inovys interface breaks new ground in commercial ATPG-ATE-failure diagnosis flows.

The direct interface between Stylus and the Encounter Test Solutions test-generation and fault-isolation tools eliminates the cumbersome fail-data translation process and preserves the information needed for diagnostics and advanced yield analysis.

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