Software to sort Sony's timing analysis: News from InTime Software

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Sony Corp has adopted InTime's Time Planner for use in its advanced SoC flow. Sony chose InTime because of its unique register transfer level (RTL) timing analysis (RTA) software that provides fast and accurate RTL timing analysis and RTL floorplanning. Time Planner supports Sony's RTL handoff flow by providing accurate timing information on the RTL code before handing it off to the chip implementation flow.

InTime's RTA-based products are unique because they provide fast and accurate RTL timing analysis on the design desktop without requiring the use of fast synthesis or other techniques that first must map the RTL into a gate-level representation.

RTA typically delivers desktop timing results 10-40 times faster than these traditional approaches.

Additionally, InTime's RTA products offer an interactive RTL debug environment that helps designers pinpoint and fix potential timing problems in their RTL code.

As a result, the RTL designer has the time to explore alternative architectures and develop an optimal RTL implementation prior to handing off for implementation.

"Sony's project development cycles and cutting-edge design concepts require the advanced design software provided by InTime Software", remarks Hiroaki (Harry) Okawa, Director and General Manager, IC Solutions Division, Innotech Corp of Kanagawa, Japan, InTime's distributor.

"In fact, Sony expects that InTimes RTA will enable its designers optimise their RTL code because of its fast turnaround on generating RTL timing reports".

RTA provides the timing accuracy and assurance that RTL designers need prior to handing off their code for implementation.

RTA provides accuracy on the timing, netlist, and physical levels.

Timing accuracy is provided with InTime RTA's use of the same LIB, LEF and Apollo input files used by standard implementation flows.

RTA also provides netlist accuracy by using the same flip-flop, latch and DesignWare inferences as full synthesis.

Physical accuracy is ensured through a spectrum of capabilities that span a physical parasitic database through placement- and obstruction-based virtual routing with full layout knowledge.

"We are pleased that Sony has chosen to adopt our RTA technology as part of its advanced SoC design flow", said Bob Smith, President and CEO of InTime Software.

"Sony has been instrumental in helping prove out the value of using RTL timing analysis in a production flow.

It is becoming clear that RTL timing analysis will play an increasingly important role in the evolving IC design flow".

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