Product category: Design and Development Software
News Release from: Innoveda | Subject: HDLScore V3.3
Edited by the Electronicstalk Editorial Team on 20 April 2001
Improved design verification
covers mixed code
Innoveda has made major extensions to its HDLScore tool for code-coverage analysis
These include untestable-code filtering; support for mixed Verilog/VHDL design environments and variable or signal coverage; and integration with the company's Visual HDL programmable register editor. HDLScore accurately measures the quality of simulation tests applied to a design through fast, thorough code coverage analysis for the entire design.
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The tool is used primarily in design verification of FPGAs, ASICs and semicustom chips.
The latest version of HDLScore (V3.3) is scheduled to be available later this month at no increase in price.
HDLScore is part of Innoveda's full family of integrated products that provide design and verification of architectures and systems.
Further reading
Innoveda returns to the Summit
Immediately ahead of its acquisition by Mentor Graphics, Innoveda has sold its system-level design (SLD) software unit to Divestiture Growth Capital (DivestCap)
HDLScore now has an untestable-code filtering capability.
Expressions containing tied or floating signals that create uncoverable entries, skewing results, are removable.
This feature gives designers a true coverage picture and also reduces simulation drag.
Coverage statistics are now back-annotated onto Visual HDL's building blocks.
This feature enables designers to view graphically from within the Visual HDL GUI what information the functional tests are gathering.
Previously, these coverage summary statistics were accessible only externally, in the text-based design environment.
Coverage statistics can also be gathered for designs containing both Verilog and VHDL source code.
Previously, designs were limited to one language.
HDLScore supports the complete design verification process from behavioural to gate-level.
With this tool, engineers have full control over when and where coverage statistics are gathered.
For portions of the design that do not need to be tested (eg re-used macros and nonsynthesisable code), the user simply "marks" HDL code so these are not included in the coverage statistics.
Coverage can be selectively turned on and off at any time.
HDLScore's comprehensive code coverage capabilities, coupled with its automatic FSM identification and extraction technology (USX), address today's HDL verification challenges without compromising project schedules.
The tool provides an accurate measure of the quality of the simulation tests applied to a design through fast, thorough code coverage analysis for the entire design.
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