Prototype validation is key to working silicon

IMS Europe has introduced a design methodology for ensuring the quick hand-off to production of complex IC and SoC designs through the validation of design performance at first silicon.

Integrated Measurement Systems has introduced a design engineering methodology for ensuring the quick hand-off to production of complex IC and SoC designs through the validation of design performance at first silicon.

The methodology extends the concept of design verification, now widely adopted within the semiconductor industry, to the validation of prototypes while the device is still in engineering development.

The IMS methodology optimises IC/SoC development and significantly impacts time-to-samples by using the original EDA design as the benchmark for verification of the virtual model and for validation of first silicon prototypes.

"Prototype testability remains the greatest single challenge facing IC/SoC development", said Chris Brigden, European General Manager for IMS' Systems Division.

"Complexity is the issue.

Complex designs require more time for test development, test debug, characterisation and failure analysis, and present the greatest problems for quick hand-off to production.

The solution is in engineering validation, which analyses failures and gives product and design engineers a clear roadmap to problem-solving".

In its technology roadmaps and in predictions of future IC/SoC development, the Semiconductor Industry Association (SIA) supports this view stating that "time-to-samples and time-to-yield are gated by test".

This statement is echoed by many semiconductor manufacturers who complain that test debug now accounts for as much as 50% of their total IC/SoC development time.

"With one in five devices offering multi-functionality on a single high-performance chip - integrating logic, analogue and memory functions - perhaps the single greatest impact on design success now lies in design validation at first silicon", continued Chris Brigden.

"By 2003, design validation may prove even more critical as SoCs are predicted to grow to three in every five devices developed".

Traditionally, engineering prototype validation has been undertaken outside the design engineering environment, where expensive production ATE systems on the factory floor has been re-programmed and adapted to the validation task.

The IMS methodology brings the prototype validation process firmly into the design engineering arena by providing product and design engineers with a dedicated engineering solution for design fault isolation, failure analysis and yield enhancement.

The result is a significant improvement in engineering productivity with higher quality, superior designs offering IC/SoC manufacturers the opportunity to be more successful, competitive and profitable.

Using a production ATE system to validate engineering designs is problematic, and new device architectures challenge the ability of the ATE to offer quality, full function validation.

The main challenge is in reprogramming the ATE - which is a "go/no-go" test system designed to quickly ascertain failures - into a fully functioning, interactive engineering validation system designed to determine why and where failures occur.

Throughput speed is used to quickly identify the general failure of the device rather than as a means to garner information about where problems are.

On a more practical level, ATE systems: take up a lot of floor space; consume huge amounts of power; require sophisticated cooling and calibration.

In contrast, the IMS methodology introduces dedicated engineering validation systems optimised for validation, characterisation, failure analysis and yield enhancement to the critical engineering phase of IC/SoC development.

Addressing very high pin counts and supporting fast device speeds, these include the Electra Mixed-Signal, Vanguard Logic IC and Orion Memory Validation Systems.

They are focused on validating the original design and performance specifications, at first silicon.

They enable design engineering teams to concentrate on speeding time-to-samples and reducing back-end, post-silicon design-cycle times and cost.

Comparatively low-cost, compact and simple-to-use compared to ATE systems, they provide repeatable and traceable results, link seamlessly to EDA tools, are small enough to fit into a engineering lab environment and mobile enough to be shared by a number of design teams, even in remote, offsite or global locations.

They enable engineers to focus on "what-if" problem-solving allowing them to establish or stretch device specifications as quickly as possible, giving instantaneous results in hours not weeks or months along with the ability to push the envelope of their designs.

They allow intuitive and interactive investigation of prototype silicon and offer the capability to debug and characterise new silicon designs quickly.

The Electra allows full coherent analysis using phase or frequency locked digital signal processing (DSP) techniques that analyse either internal circuit blocks, or cells and full multi-block system functions.

DSP instrumentation covers a very wide analogue dynamic range and spectrum, providing static and dynamic analysis in time, frequency and phase relationships within a mixed signal environment.

The Vanguard collects and displays all digital pin data, allowing full logic analysis in one pass.

Device speed path errors can be easily interrogated and interactively analysed using cycle stretch and shrink adjustments to the drive data.

The same tool can be used to stretch digital performance beyond the original specifications.

The Orion is a high-speed, low cost engineering system aimed at the memory device market.

Orion provides DRAM, SRAM, SDRAM, DDR SDRAM and RAMBUS chip manufacturers with unmatched speed and ease of use to quickly characterise and verify advanced memory devices.

"Design teams want easy-to-use software optimised for the type of testing needed to validate the IC design", concludes Chris Brigden.

"As with any dedicated toolset, they want the engineering system's design verification and characterisation software tools to consider the source EDA information and format, to translate this data into useable pattern data, then allow easy manipulation of the data for "what-if" analysis.

They just want to design products and debug them as fast as possible in the engineering analysis lab using simple, intuitive tools".

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