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News Release from: IEEE P1581 Working Group
Edited by the Electronicstalk Editorial Team on 19 April 2007
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The IEEE P1581 has set up its working group to define a low-overhead design-for-test methodology to be implemented in memory devices.
The IEEE P1581 working group is defining a low overhead design-for-test (DFT) methodology to be implemented in memory devices for the support of board- and system-level connectivity test Additionally, P1581 proposes standard means of access to other (optional) on-chip resources, such as device identification, built-in self test (BIST) and/or built-in self repair (BISR) circuitry