Product category: Communications ICs (Wired)
News Release from: IDT | Subject: 72P51767L6BB and (72P51777L6BB
Edited by the Electronicstalk Editorial Team on 7 June 2005
Flow-control chips speed past 10Gbit/s
Integrated Device Technology has developed a new family of flexible 10Gbit/s Multi-Queue flow-control (FCM) ICs
The new devices offer densities of 5 (72P51767L6BB) or 10Mbit (72P51777L6BB), and support high-speed operations exceeding 10Gbit/s, using clock rates up to 166MHz DDR (double datarate). Configured with the x40bit databus, these Multi-Queue flow-control devices offer data throughput of up to 13.3Gbit/s.
This article was originally published on Electronicstalk on 7 June 2005 at 8.00am (UK)
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The Multi-Queue flow-control devices support the quality of service needs of next-generation, high-throughput platforms, such as W-CDMA basestations, large-scale data acquisition systems, high-speed image processing equipment and 10G/1G Ethernet switch/routers, including jumbo packets as large as 9Kbyte.
Further, because of the high throughput supported by the Multi-Queue flow-control devices, customers could use these devices with only one queue, much like a large, DDR first-in, first-out (FIFO) memory device, to support very fast buffers in the data stream.
Increasing queuing flexibility and enabling easier implementation for data packets, IDT has added a unique feature mode that allows users to monitor any of the pins when receiving packets, giving the designer time to react to any indication, such as customer definable end of packet (EOP).
Further, the Multi-Queue flow-control devices are flexible enough to remember the EOP mark and ensure no data is lost when the queue is accessed again.
The new Multi-Queue flow-control devices have an internal phase-locked loop (PLL) that enables the device to offer a source synchronous output read clock (echo clock) that centre aligns the output read data for downstream devices.
The echo clock decreases read data access time to 0.5ns and allows the Multi-Queue flow-control devices to operate at high DDR frequencies to meet 10Gbit/s line rates.
The new devices also deliver the same value-added features as the innovative 4Mbit Multi-Queue family including: bus matching; frequency matching; configurable queuing; user-selectable I/O; programmable empty, partially empty, full and partially full flagging; and 'mark and rewrite' and 'mark and reread'.
Other technical highlights include electrical compatibility to the 802.3ae XGMII specification for passive interconnection to 10G Ethernet devices; programming of any number of queues up to 128, with six default settings; a 1.8V core to conserve power; and expansion to any number of queues and any number of chips.
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