Product category: Programmable Logic Devices
News Release from: IDT | Subject: VersaTime
Edited by the Electronicstalk Editorial Team on 6 July 2004
Programmable timers add system flexibility
A new family of highly versatile programmable timing devices is aimed at a wide range of applications in the communications, storage, digital consumer and industrial markets
The innovative VersaTime product family represents the industry's first complete portfolio of programmable skew and zero delay buffers with nonvolatile programming capability, allowing customers to consolidate and replace the large number of dedicated fixed function clock devices used today to build timing networks.
This article was originally published on Electronicstalk on 6 July 2004 at 8.00am (UK)
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In addition, the VersaTime programmable clock family comprises the first timing products to offer an IEEE1149.1a compliant JTAG interface that not only enables its inclusion in design-for-test (DFT) infrastructure but also supports device programming within the same scan chain.
This innovation empowers customers to program and test their timing networks using the same infrastructure already in place for other devices, such as programmable logic and nonvolatile memory.
The support for in-system programming provides superior flexibility by allowing device configuration at any point in a product's life cycle.
Unlike alternative products, the IDT VersaTime programmable clocks do not compromise on jitter performance.
The new family achieves low cycle-to-cycle jitter of less than 75ps peak to peak (maximum value with outputs at the same level) and 100ps peak to peak (maximum value with outputs at different levels) - numbers that are less than half those of competing solutions.
The flexibility of the VersaTime programmable clocks allow the devices to be used for a combination of clock generation and distribution functions.
A JTAG or I2Cbus serial interface is provided for device programming, and an internal EEPROM allows the user to save and restore the configuration of the device.
Programming kits, software and development tools are available.
The family's DFT capability eliminates the need for a dedicated infrastructure, currently needed to create "boundary scan equivalent" circuits for timing devices.
Bank selectable signal translation is also provided, eliminating the need for additional timing devices to interface between various I/O types.
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