Product category: Memory Devices and Modules
News Release from: IDT | Subject: TeraSync DDR FIFO family
Edited by the Electronicstalk Editorial Team on 22 February 2002
FIFOs feature double datarate capabilities
Acording to IDT (Integrated Device Technology), the high-performance TeraSync DDR FIFO family is the industry's only FIFO family with double datarate capabilities
Designed to offer the next level of performance, this family of devices offers clock cycle speeds up to 250MHz and targets data rates up to 40Gbit/s, more than doubling the bandwidth currently available for leading-edge applications in the enterprise and carrier-class markets. The TeraSync DDR FIFOs are optimised for Sonet, Fibre Channel and Gigabit Ethernet, as well as image processing and instrumentation applications.
This article was originally published on Electronicstalk on 22 February 2002 at 8.00am (UK)
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When using two TeraSync DDR FIFOs in parallel, this solution also provides the industry's most efficient means for applications to implement OC-768 line-rate buffering.
By conserving input/output (I/O) pins and reducing the clock frequency by half, the devices achieve 500Mbit/s bandwidth per pin and consume less board space than any other off-the-shelf solution.
The family offers is available in densities from 512Kbit (IDT72T4088) to 5Mbit (IDT72T20128), and is offered in a unique set of x10, x20 and x40 configurations, allowing the system to denote valid bytes and perform packet delineation.
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In addition to its traditional FIFO functionality and double datarate capabilities, the TeraSync DDR FIFO family delivers extremely low power consumption and an advanced set of features.
The devices offer bus-width matching and rate matching, including double datarate to single datarate matching, which allows one port of the device to operate in double datarate mode, while the other port operates in single datarate mode.
TeraSync DDR FIFOs also supply user-selectable I/Os on both ports, supporting 2.5V LVTTL/ LVCMOS with 3.3V tolerant inputs, 1.8V LVCMOS/eHSTL and 1.5V HSTL.
IDT's TeraSync DDR FIFO devices also support source echo read clock and enables, as well as a retransmit from mark function.
The echo clock feature allows interfaces to run at speeds up to 250MHz by controlling the phase and timing relationship of the output data and clock signals.
The devices are available in 208-ball BGA packages and include a JTAG interface for debugging and test.
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