Product category: Design and Development Software
News Release from: Chip Estimate Corp | Subject: Time Architect
Edited by the Electronicstalk Editorial Team on 7 October 2003
Virtual prototypes predict SoC viability
Time Architect is a new class of electronic system level virtual prototype software for fast, accurate estimation of chip size, power, cost and yield
Time Architect is a new class of electronic system level (ESL) virtual prototype software for fast, accurate estimation of chip size, power, cost and yield. Time Architect provides the umbrella over ESL design common in today's high-end ICs and opens a new software category for the EDA industry.
This article was originally published on Electronicstalk on 7 October 2003 at 8.00am (UK)
Related stories
Nonvolatile memory joins IP catalogue
Sidense is enabling centralised access to information about the company's embedded, nonvolatile memory SiFuse and SiPROM IP cores at ChipEstimate.com
Software predicts IC size, power and cost
Novel technology enables performance analysis at the earliest phase of the chip design cycle
It allows electronic specification development for complex SoCs with full knowledge of the IC supply chain of libraries, memories and intellectual property.
Specification can be evaluated for cost, size and power requirements.
Finally, it obsoletes traditional IC-estimation methods that have evolved from pencil and paper to spreadsheet.
"Given the complexities of today's silicon, smarter tools are needed", remarks J George Janac, Giga Scale IC founder, CEO and Chairman.
"A single foundry may have more than 50 library alternatives, hundreds of memory generators, thousands of pieces of IP.
Further reading
Memory IP company joins prime IP partner program
Memory IP designer joins IP partner program to make available its technology including encryption keys, access and authentication codes, and high-bandwidth digital content protection (HDCP) keys
Newsletter tells all on the latest IP
Biweekly online newsletter aims to serve the growing community of designers using semiconductor intellectual property in their chip designs
IP partnership formed
IC Nexus has partnered with Chip Estimate Corporation and joined its Prime IP Partner Program
We are focused on giving users new capabilities to see the implications of their choices before diving into implementation".
Replacing spreadsheet calculations, Time Architect is a comprehensive and easy-to-use electronic specification capture and estimation system.
It is available in a web-enabled version that brings together far-flung information from IC libraries and IP catalogues.
Time Architect is based on Giga Scale ICs proprietary Technology Macro Modeling (TMM) for three to nine layers of metal, and process feature sizes ranging from 90nm to 0.25um.
TMM interprets standard data LEF or Liberty, for example describing semiconductor processes, libraries and IP to produce accurate macro models for area, power, clock and density evaluations.
Every design today contains some ESL, register transfer level (RTL) source code and analogue design components.
SoCs are designed with licensed libraries, purchased memories and IP blocks from numerous vendors.
Providing a system that can display the economic model is critical to the design process and helps reduce risk.
"Time Architect's calculation helps us decide which system components can remain in as programmable devices and those that can be produced as chips", says Larry Thomson, CEO of Anchor Bay Technologies, provider of systems components for video processing.
"Giga Scale IC-provided datasets give us the freedom to evaluate different technologies and concentrate on our business without having to constantly hunt for data models".
Time Architect presents users with the ability to create a specification electronically.
Designs are composed of reused components, licensed IP blocks, and memories.
Giga Scale IC bundles Time Architect with extensive library datasets and IP catalogues.
Users have access to IP vendors through a browser.
Datasheets for IP blocks can be accessed from the Internet or from a cache.
Specifications can be configured from multiple IP vendors without quitting the tool.
Electronic specifications are configured by defining clocks, activity, I/O signals, voltage zones and other parameters.
IP in the specification is assigned to these providing for accurate power and size estimation.
Estimates of wiring, usage and clock networks provide a means to accurately model the final design for size, power and yield.
Two thirds of most designs are composed of I/O cells, memories and IP blocks whose area is known to Time Architect.
Correct specification can yield an estimate within a few percentage points.
Standard cell areas are estimated by modelling the number of layers to carefully compute cell routing usage.
Modelling of clock networks and special resources provides accurate estimates of random logic areas.
Yield and cost can be estimated through entry of the latest foundry data.
Chip size estimates are mapped onto a user-selected wafer to calculate the available number of die of a particular design will yield.
Users can enter wafer cost and yield parameters from the foundry.
Time Architect can calculate an estimate of the number of good die and cost per die.
Cost and power can then be checked against project requirements.
Time Architect is available in a web-enabled or stand-alone configuration.
Platform support is provided for any Windows, Sun, Linux, or Mac OS X machine.
Pricing for Time Architect with library datasets starts at US $20,000 per year.
• Chip Estimate Corp: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• NEW
• Electronicstalk Home Page
Related Business News
Icoa Is Partnering With Anchorfree To...
...Enhance And Monetize Thousands Of Wi-fi Hotspots. Icoa, Inc., a national provider of wireless broadband Internet access and managed network services in high-traffic public locations, and AnchorFree Inc., a rapidly growing Wi-Fi community powered by advertising, have announced today that they are partne
Olympics raises demand for IT contractors
The number of IT contractors working in the engineering sector has almost doubled in 12 months because of demand generated by the 2012 Olympics, according to contractor Giant Group PLC.
Stellar Appoints CIO to Lead Call...
...Centre Outsourcing Technology Strategy. Stellar, a leading global business process outsourcing provider, today announced that Warwick Marx has been appointed Chief Information Officer of Stellar Asia Pacific.
Dell pushes for better Linux drivers
Dell wants to see better software drivers for Linux so that the firm can ship more notebooks and desktops running the operating system, according to one of its software engineers.
Eds Sales Take A Tumble
Dave Friedlos, Computing , Thursday 17 May 2007 at 00:00:00 But experts say downturn may reflect market weakness, writes Dave Friedlos Outsourcing giant EDS has released disappointing first-quarter figures showing slower growth and fewer con
Search the Pro-Talk network of sites
