Product category: VMEbus Boards and Assemblies
News Release from: GE Fanuc Embedded Systems | Subject: ICS-8551
Edited by the Electronicstalk Editorial Team on 22 November 2007
Mezzanine makes light of software
defined radio
ADC PMC/XMC module offers both two- and four-channel operation for software defined radio applications such as spectrum monitoring, signal intelligence, tactical communications and radar.
The ICS-8551 is a rugged ADC PMC/XMC module that offers both two- and four-channel operation with sampling frequencies of 1.5GHz (four channel) or 3GHz (two channel) for software defined radio (SDR) applications such as spectrum monitoring, signal intelligence, tactical communications and radar The combination of high performance ADC and FPGA resources allows VHF and UHF signals to be digitised and processed directly on the ICS-8551
This article was originally published on Electronicstalk on 23 Jun 2006 at 8.00am (UK)
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Algorithms such as digital down conversion, FFT, and filtering can be developed to execute in the onboard Xilinx Virtex-4 FPGA (XC4VFX60 or XC4VFX100), using the included hardware development kit (HDK).
"The ICS-8551 further extends our industry-leading range of software defined radio solutions, pushing back the boundaries of sampling frequency in the XMC format", says Jonathan Jones, Sensor Processing Technology Leader at GE Fanuc Intelligent Platforms.
"With its combination of high performance, compact size and available ruggedisation, it is ideal for the most demanding ADC applications in both military and commercial environments".
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PowerPC-based cPCI board boasts more flexible I/O
6U CompactPCI single board computer uses a 1GHz MPC7447A or 1.4GHz MPC7448 Freescale processor and extensive I/O ports for improved performance and flexible, rugged functionality.
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AdvancedMC module is one of the first cost-effective packet processors that is available now for customers, and is ideal for compact MicroTCA systems.
For maximum application throughput, the ICS-8551 provides the user with up to eight lanes of high-speed serial I/O, at rates up to 3.125Gbyte/s, for communication with XMC-equipped carrier cards such as the GE Fanuc Intelligent Platforms V4DSP front end signal processor.
The 64/66 PCI interface provides sustained datarates in excess of 400Mbyte/s, and the Pn4 user I/O port allows the user to define direct point-to-point connections to the FPGA, eliminating interrupt latencies.
The latter two interfaces may be used for applications in which the XMC interface cannot be used.
The ICS-8551 HDK includes both a default logic core and a digital down-convertor (DDC) IP core.
The default logic core, designed to provide minimum occupancy of the FPGA, provides a basis for customers to program their own functionality.
It includes an A/D interface and data buffering to the high-speed serial outputs and to the PCI bus, via FIFO buffers.
The DDC core enables a band-limited signal at a given (programmable) Intermediate frequency to be shifted in frequency to base band, then filtered and decimated prior to output.
Output options include the high-speed serial outputs or the PCI bus.
Other features including protocol cores will be added to the HDK in future.
Software development kits for the ICS-8551 are available for the VxWorks, Linux and Windows operating systems.
Each SDK includes a kernel level driver, full API and application example code written in C.
A Flash Loader utility is included to enable users to load FPGA cores to the onboard Flash memory over PCI bus.
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