Product category: Memory Devices and Modules
News Release from: GD Technik | Subject: 32Mbit synchronous SRAMs
Edited by the Electronicstalk Editorial Team on 16 January 2001
Highest density for
32Mbit synchronous SRAMs
Three new 32Mbit synchronous SRAMs that give the highest density available in a single package are being introduced by design-in specialist GD Technik
The devices from White Electronic Designs are available in speed ranges from 100 to 166MHz, making them ideal for high end networking applications such as Gigabit/Terabit Ethernet, ATM switches, add/drop multiplexers and optical switches. All three devices are housed in 17 x 23mm, 119 BGA packages.
This article was originally published on Electronicstalk on 16 January 2001 at 8.00am (UK)
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The WED2ZL361MS-BC and WED2ZL361MV-BC are 2.5 and 3.3V versions, respectively.
They both offer 1M x 36bit NBL (no bus latency) synchronous SRAM.
Each integrates two 1M x 18 SRAMs into a single package.
The WED2ZL236512S-BC is a 2.5V version configured as two banks of 512K x 36, offering a lower power solution for power constrained systems.
The new synchronous burst family employs high speed, low power CMOS designs that are fabricated using an advanced CMOS process.
The NBL synchronous SRAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycles when there is a transition from read to write or vice versa.
All inputs are synchronised to rising clock edges, with the exception of output enable and linear burst order.
Asynchronous inputs include sleep mode enable.
Write cycles are internally self-timed and initiated by the rising edge of the clock input.
This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals.
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