Product category: Intellectual Property Cores
News Release from: GDA Technologies | Subject: GPEX
Edited by the Electronicstalk Editorial Team on 19 September 2003
PCI Express IP core
works on ASICs or FPGAs
The GPEX is a new PCI Express IP core that provides the computing, networking and communications industries a significant enabler for development of silicon based products supporting PCI Express
The GPEX is a new PCI Express IP core that provides the computing, networking and communications industries a significant enabler for development of silicon based products supporting PCI Express architecture. The GPEX is a rich featured and highly flexible core supporting endpoint, root complex, switch, and bridge applications.
This article was originally published on Electronicstalk on 19 September 2003 at 8.00am (UK)
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GPEX's architecture is carefully tailored to optimise link usage, latency, reliability, power consumption, and silicon footprint for both ASIC and FPGA implementations.
"We are committed to providing our customers cost-effective, compliant and interoperable PCI Express IP products", said Prakash Bare, Vice President of IP Business at GDA Technologies.
"Our extensive experience in developing high performance IP cores for compute and networking interfaces has played a significant role in creating GPEX which delivers unprecedented performance, configurability, and scalability features to a wide variety of applications".
"Wide availability of PCI Express IP from companies like GDA promotes faster time to market for companies developing PCI Express components", said David Formisano, Ecosystem Initiatives Manager in the Communications Infrastructure Group at Intel.
"This enables companies to migrate products to PCI Express more rapidly than was possible with previous technology transitions".
The GPEX adheres to the PCI Express 1.0a specifications and is available for both ASIC and FPGA implementations.
It supports endpoint, bridge, switch and root complex solutions.
It includes MAC, data link and transaction layers.
The GPEX supports a PIPE based PHY architecture and provides a flexible packet oriented user logic interface with an optional DMA controller.
GPEX Configurable options include number of lanes (up to 16), number of virtual channels (up to eight), maximum payload size (up to 4Kbyte), and transmit retry/receive buffer size.
The GPEX provides flow control support for both directions and completely handles PCI Express ordering rules.
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