Arrays aim for mid-volume ASIC market: News from Fujitsu Microelectronics Europe

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AccelArray technology aims to meet customer requirements for low cost and minimal design cycles using Fujitsu's proven design and process technology leadership. AccelArray shortens the design and fabrication cycle times of a typical standard cell ASIC by as much as 70%, and reduces total ASIC development cost for 0.11-micron products by as much as 80%. The new technology combines the performance of ASICs with the flexibility of FPGAs.

It supports 333MHz core system frequency, with 800MHz analogue PLL capability.

Available AccelArray gate counts range from 512,000 to 3.8 million.

Using AccelArray, back-end physical design can be completed from two to four weeks and manufacturing prototypes can take as few as two weeks.

Customers can receive prototypes in only eight weeks, compared with the currently typical schedule of 28 to 32 weeks.

AccelArray targets storage networking, telecommunications and industrial automation applications, which need the high performance of cell-based ASICs, and typically have volumes of between 5000 and 100,000 units per year.

"Customers want to optimise their time-to-market and the total cost of product ownership.

AccelArray delivers the reduced cost, improved time to market and lower cost of ownership the industry now requires", said Dirk Weinsziehr, Senior Director Marketing for Fujitsu Microelectronics Europe.

"Our approach reduces their NRE costs, which have increased as design and manufacturing processes move to deep submicron technology.

Increases in NRE have had an adverse impact on the number of new ASIC designs", he added.

AccelArray is built on Fujitsu's proven 0.11-micron technology.

Customer designs can be implemented using three metal mask layers.

The AccelArray platforms support pre-defined high-speed interface I/Os that deliver key system functions, enabling customers to avoid long design-cycle times and to focus their resources on the differentiating elements of their product design.

The AccelArray architecture has been designed specifically to simplify physical design tasks.

It delivers easy timing closure with built-in I/O interfaces, and incorporates pre-designed global clock trees and 24 flexible peripheral local clocks.

This platform also solves signal and power integrity issues such as crosstalk and IR drop.

Built-in logic scan, JTAG and RAM BIST ensure simplified back-end physical design.

Customers of the AccelArray technology will have access to the advanced intellectual property in Fujitsu's IPWare portfolio.

The first pre-fabricated platforms for use on the AccelArray technology, including a wide range of SRAMs, flip flops and ASIC logic, are ready now with more to be added shortly.

Vertical market platforms include embedded high-speed I/O macros such as SPI-4, SFI-4, SFI-5, XAUI, Fibre Channel and Rapid I/O, all of which will be available soon.

"AccelArray builds on Fujitsu's legacy of delivering dependable, cost-effective technology to our customers", said Mark Ellins, ASIC Marketing Manager Europe at Fujitsu Microelectronics Europe.

"By adding the AccelArray technology to our portfolio, we extend our ASIC reach to more customers in the mid-volume market".

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