News Release from: Fujitsu Microelectronics Europe
Edited by the Electronicstalk Editorial Team on 21 June 2002
Multichip module shrinks to single-chip size
Fujitsu has developed the world's first prototype chip-size module (CS Module), incorporating advanced system-in-package technology.
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Fujitsu has developed the world's first prototype chip-size module (CS Module), incorporating advanced system-in-package (SiP) technology. The technology enables the multichip package to be shrunk to the size of the largest chip integrated within it. The CS Module has been developed though advances in Fujitsu's ultra-thin wafer processing, redistribution and chip stacking technologies.
Chip-size-module technology now offers the system designer the ideal system LSI solution for use in a host of miniaturised equipment.
Through the continued need for compactness and increased functionality in mobile phones, personal digital assistants (PDAs) and digital audio/video equipment, there is a relentless demand for System LSI solutions which offer the smallest size and shortest development times.
Conventional System LSI uses system-on-chip (SoC) methodology, which integrates multiple functions on a chip.
The alternative system-in-package (SiP) approach, which allows separate die wafers to be stacked on the substrate, uses existing package assembly techniques which drive down both development lead times and costs.
The conventional SIP approach does however suffer from the need for both an interposer, such as a tape carrier substrate, and fine pitch interconnection, such as wire bonding or flip chip.
The new CS Module uses Fujitsu's established redistribution technique for the development of ultra-thin wafer-level processing together with high accuracy chip mounting and inter-chip filling technologies.
Ultra-thin wafer processing is a special wafer support technology, which allows chips to be polished down to a thickness as low as 25 microns.
The gap between the thin chips is filled using this inter-chip insulation technology, which enables a redistribution trace to be formed to connect inner and outer pads electrically.
With this approach, the need for an interposer and fine pitch interconnection is eliminated.
The technology also allows inductive and capacitive elements to be embedded in the module.
While retaining the short development cycle and low cost benefits of conventional SiP, CS Module technology also significantly reduces package size.
Compared with existing SiPs with similar functionalities, the prototype CS Module offers a 30% reduced board area and 65% thinner profile.
Chip-size-module technology will now enable System LSI to be designed and manufactured integrating logic, analogue and memory functions, often using different process technologies and operating voltages, into the very smallest SiP for very high density, high-end applications.
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