News Release from: Forte Design Systems
Edited by the Electronicstalk Editorial Team on 24 January 2006

System level synthesis supports SystemC TLM

Cynthesiser v3.0 is the first ESL synthesis product to add support for SystemC transaction level model synthesis and automated power optimisation.

Note: Readers of the Editor’s free email newsletter will have read this news when it was announced. . It’s free!

Forte Design Systems has announced the availability of the next generation of its Cynthesiser electronic system level (ESL) synthesis product. Cynthesiser v3.0 is the first ESL synthesis product to add support for SystemC transaction level model (TLM) synthesis and automated power optimisation. 'The transaction level is a substantially higher level of abstraction than standard behavioural level, and its advantages are compelling', said Brett Cline, Vice President of Forte's Customer Operations and Services Group.

'Version 3.0 of our industry-leading Cynthesiser not only further raises the abstraction level available to system and hardware designers by allowing them to create and implement arbitrarily high levels of abstraction, but our automated power optimisation sets the bar for ESL synthesis capabilities'.

Designers commonly run transaction level models today for verification of complex ASIC and SoCs.

The abstract communication mechanisms used in TLM, typically referred to as channels, pass information between design blocks by separating the interface from the algorithm and abstracting cumbersome hardware interface details from the designer while maintaining data coherency between the blocks.

This standard modelling methodology raises the abstraction level and allows the designer to model the design much more quickly and significantly increases simulation performance about 25 times over pin-level behavioural and around 100x over RTL.

It also establishes one verification environment for verifying the design at both TLM level and RTL level; any hardware block can be verified as soon as it is implemented.

Forte's TLM synthesis represents the first behavioural synthesis offering to integrate high-speed SystemC TLM models with the implementation flow, maintaining a common source for simulation and implementation.

Cynthesiser automatically creates high quality RTL from the TLM representation by adding bus specific cycle-accurate pin-level hardware interface details.

Because the process is automatic and fast, designers can easily change I/O interfaces to retarget target their IP to a number of different interfaces eliminating costly rewriting and risk and to explore how various interfaces affect the overall quality of results.

To further help the designers achieve results quickly, Forte is providing synthesisable behavioural IP for FIFOs, memory interfaces and streaming interfaces.

Additionally, OSCI has recently added a set of classes in SystemC for TLM, in effect extending the vocabulary of design to include high-level communications.

Forte's TLM synthesis directly supports the OSCI TLM library, and can be customised by Forte or by the user to support other TLM environments.

Acceptable power characteristics are paramount to the success of many ASIC and SoC designs today, especially at 90nm and below.

Historically, optimisation has typically been done in RTL at the end of the design cycle, where changes are often difficult and expensive.

Cynthesiser v3.0 adds support for power optimisation early in design - during the high-level synthesis process - using well-known techniques such as clock gating.

Designers can now easily create multiple candidate RTL implementations which tradeoff area, performance, and power by directing Cynthesiser to meet certain design constraints in minutes rather than weeks or months.

This gives designers the ability to pick the right implementation for their specific design constraints - a capability not available using RTL.

Cynthesiser v3.0 adds support for Summit Design's Vista IDE for SystemC.

Designers will be able to use Vista to quickly debug and verify behavioural design models and then pass models directly to Cynthesiser through its automation environment.

Additionally, Cynthesiser v3.0 has a number of enhancements which further improve QoR of the RTL output and expands the synthesisable input available to the designers.

Cynthesiser v3.0 is available immediately starting at US $250,000 for a 1 year time-based licence.

The TLM Synthesis and Power Optimisation features are available as addons to Cynthesiser starting at US $65,000 and US $90,000, respectively.

• Forte Design Systems: contact details and other news
• Other news in Design and Development Software
• Email this news to a colleague
•
• RSS news feed for Forte Design Systems
• RSS news feed for Design and Development Software
• Electronicstalk Home Page

 
Advertisers! Download our free 2006 media pack now