Software manages complex timing interfaces: News from Forte Design Systems

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The release of the TimingDesigner interactive timing analysis and diagram product brings focus to the project management challenges of designing complex timing interfaces. More stringent specifications for high speed designs means that timing analysis must now incorporate signal integrity and physical effects, as well as manage and monitor timing margins through the design process. Chronology's TimingDesigner allows users to model their timing challenges via timing diagrams and spreadsheet technology, and analyse a range of conditions to obtain accurate timing results.

Designers can define timing constraints, evaluate timing parameters, create specifications, and analyse complex interfaces within their design.

Today, timing margin information changes frequently throughout the course of a design project - too often it is miscommunicated among engineering teams because it is manually extracted from documents or reports.

TimingDesigner 7.0's new project manager simplifies the exchange of critical timing information and enables users to better manage the specification and analysis of high performance interfaces for their digital IC and board designs.

To handle growing design complexity, designers now have the option to logically organise multiple diagram components within one project.

Components and blocks are arranged and displayed in a single tree, with a summary list of all constraint violations in the project diagrams.

Designers can also merge two diagrams from different components - automatically creating an interface that accounts for component connectivity as well as managing signal duplication and propagation delays.

"With double-datarate interfaces commonly running speeds in the 350MHz-plus range, doing a comprehensive timing analysis is a must", said Dean Moss, Senior Applications Engineer of Xilinx.

"TimingDesigner has helped us prove out complex timing relationships and allows our customers to verify that their interfaces will work with our FPGAs before they go to layout".

"The new project management capabilities of TimingDesigner 7.0 are the right next step for handling the growing complexity of high-speed interface design".

"For timing-critical designs, we needed to provide our customers with a logical way to organise multiple timing diagrams as components within a single project", said Jacquie Taylor, General Manager of the Chronology Division, Forte Design Systems.

"TimingDesigner 7.0 offers designers a new way to manage complexity by aligning their timing plan in the same way they organise their designs, whether they are looking at interfaces between embedded functions on an ASIC or a programmable IC, or between devices on a circuit board".

A number of other enhancements are included in this release.

Designers can now localise library management for specific diagrams and their associated paths, avoiding time-consuming network access to large library repositories.

Additionally, to simplify analysis and save debug time, designers can now designate the use of only minimum or maximum values for their diagrams (as opposed to both minimum and maximum values) to perform best-case and worst-case timing analysis.

Other enhancements include: waveform dividers to visually group signals together; font modifiers to better support documentation style guides; display of decoded values on valid edges of signals, derived signals, and buses; and new built-in spreadsheet functions for improved analysis reporting.

TimingDesigner 7.0 is available now.

Chronology offers several licensing options including perpetual and time-based.

Pricing starts at $2640 depending on the configuration.

TimingDesigner is supported on the Microsoft Windows, Sun Solaris, HP-UX and Linux platforms.

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