Product category: Intellectual Property Cores
News Release from: Faraday Technology | Subject: FA626TE
Edited by the Electronicstalk Editorial Team on 15 August 2007
ARM core overcomes speed restrictions at
90nm
32bit RISC processor with eight pipeline stages has separate instruction/data caches and scratchpads, a write buffer, a memory management unit and a JTAG ICE interface.
Faraday Technology has launched its first ARM v5 instruction set architecture (ISA) compliant processor - FA626TE, a 32bit RISC core with excellent computing and power-efficient capabilities This powerful processor is specially designed to target the applications like infotainment, PNDs (portable navigation devices), IP set-top boxes, industrial PCs, high-speed networking and storage SoCs
This article was originally published on Electronicstalk on 2 Feb 2007 at 8.00am (UK)
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The first hard core, which reaches a worst case clock speed at 533MHz, is available now on the UMC 0.13um process.
Faraday expects its next versions for 90nm at UMC, running 667 and 800MHz in worst case, to be available in early Q4 and the end of 2007, respectively.
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From the emerging One-Laptop-Per-Child (OLPC) programme to the small but powerful convergence mobile devices, the ARM CPU is at the heart of the computational processing.
Therefore, there is an incessant need for high performance processors, even for small consumer devices.
For ARM's v5 ARM9 family, to reach any speed beyond 650MHz is only possible using 65nm semiconductor processes; however, that entails very expensive mask costs and lengthy manufacturing time.
Faraday's FA626TE is designed to enable 667 and 800MHz clock speed in today's mainstream 90nm process.
"We are very glad with the delivery of this high differentiated v5 processor core", says Charlie Cheng, Vice President of Marketing at Faraday Technology.
"As one of just a few architectural licensees in the ARM ecosystem, it's our responsibility to expand the ARM ISA into new territories, and in this case, reaching beyond 800MHz to encroach into PowerPC and x86 architecture territories", he adds.
Faraday is experienced in microarchitecture design, synthesis expertise, and optimised layout capability, which are all key factors contributing to the provision of the FA626TE in such a short time.
The FA626TE processor, a 32bit RISC with eight pipeline stages, has separate instruction/data caches and scratchpads, a write buffer, a memory management unit, and a JTAG ICE interface.
The FA626TE CPU core uses four AHB or AXI interfaces with configured 32/64bit widths to communicate with external memory and devices.
For designers, the fully synthesisable core and the single-phase clock based architecture especially make the SoC integration a very easy task.
"To meet the high clock requirement of the powerful 800MHz FA626TE, we overcome the process and micro-architecture limitations by implementing several advanced design techniques", says Thomas Hsieh, Associate Vice President of Central R and D at Faraday.
"We're developing the solution by using data path optimisation, process tuning, specific library and bin sorting to improve core clock speed, but preserves portability, and ease-of-integration".
"That's how we could implement the ultra high performance FA626TE processor which enables the 800MHz speed in 90nm process", he adds.
The first hard core which reaches the worst case clock speed at 533MHz is available on the UMC 0.13um process.
Faraday expects its next versions for 90nm at UMC, running 667 and 800MHz in worst case, to be available in initial Q4 and the end of 2007, respectively.
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