Product category: Electronics Manufacturing Services
News Release from: EDA Solutions | Subject: IBM 65nm MPW
Edited by the Electronicstalk Editorial Team on 23 April 2007
Shared wafers offer
access to 65nm process
Chip designers can fabricate devices on IBM's 65nm silicon foundry process using the Mosis multiproject wafer service, available in the UK from EDA Solutions
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Mosis is offering access to IBM's 65nm silicon foundry process through its multiproject wafer (MPW) service. The service means that system-on-chip designers can obtain samples or small production quantities of digital or mixed-signal devices at less than 10% of the cost of using a dedicated production run.
Sharing masks and wafers with other chip designs achieves this.
Mosis also offers die packaging and test.
65nm is the smallest process geometry presently available through MPW services.
It is typically used for high-performance, high volume applications in wired and wireless communications, and in digital media.
The process is also suited to very low power chip designs.
Users of the Mosis service pay only for the silicon area occupied by their designs; costs are not shared equally based on the number of users.
Deputy Director of the Mosis service, Wes Hansford, comments: 'Many chip designers still believe that it takes millions of dollars to create a submicron design using a leading-edge process'.
'This is restricting innovation'.
'The Mosis service removes the barrier and makes access to leading-edge processes affordable'.
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