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Product category: Design and Development Software
News Release from: EDA Solutions | Subject: T-Spice v11
Edited by the Electronicstalk Editorial Team on 28 July 2005

Simulator covers sub-100nm process
MOSFETs

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T-Spice v11 is the latest version of the analogue circuit simulation platform from Tanner EDA.

T-Spice v11 is the latest version of the analogue circuit simulation platform from Tanner EDA This newest release adds support for the latest Berkeley BSIM models up to the v4.4.0 release that allow users to accurately simulate MOSFET physical effects down to the sub-100nm range

This latest release also supports numerous advanced modelling features to improve simulation accuracy.

New modelling features supported include gate and body resistance networks for RF modelling, non-quasi-static (NQS) model, comprehensive geometry-based parasitic models for multi-finger devices, and stress effects modelling.

Support for BSIM SOI v3.2 helps designers using the SOI CMOS process.

It allows them to accurately model partially depleted, fully depleted and unified FD-PD SOI devices.

Self-heating and RF resistor networks can also be modelled.

MOSFET EKV support assists designers needing a continuous, physics based MOSFET model for low power analogue and mixed analogue-digital circuit design.

Tanner EDA's T-Spice v11 also includes improvements to the VBIC model with addition of self-heating effects and improvements to BSIM3 v3.2.4 including stress effects modelling and enhanced diode and temperature equations.

These functions improve compatibility with many foundry model libraries.

T-Spice V11 is available now.

Depending on configuration, Tanner EDA products are priced starting at US $5000 per seat and are available with either networked or node-locked licensing.

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