News Release from: Cypress Semiconductor
Edited by the Electronicstalk Editorial Team on 11 February 2003
Software speeds CPLD design
The latest release of the Warp design tool includes a new timing constraints specification capability, faster run-time, improved project management and wider support for Cypress's CPLD families.
Note: Readers of the Editor’s free email newsletter will have read this news when it was announced. . It’s free!
The latest release of the Warp design tool and environment from Cypress Semiconductor includes timing constraints specification capability, faster run-time, improved project management and expansion of support for Cypress's industry-leading family of complex programmable logic devices (CPLDs). With over 28,000 software seats in place around the world and used in over 150 universities, the Warp development tool is one of the most popular HDL-based CPLD development tools in the world. Powerful and easy-to-use at every step in the development process, Warp R6.3 supports all of Cypress's programmable logic devices, including the Delta39K and Ultra37000 CPLD families and the Programmable Serial Interface (PSI) family of physical layer (PHY) devices.
Warp R6.3 enables designers to develop programmable PHY solutions for next-generation communications systems in the InfiniBand, Escon, Fibre Channel, gigabit Ethernet and SMPTE markets.
"With a comprehensive design, synthesis, and simulation environment, the latest Warp R6.3 development tool offers complete software support for CPLDs", said Rajiv Nema, Product Marketing Manager for CPLDs at Cypress.
"Warp R6.3 provides the capabilities of tools costing much more, enabling designers to capitalise on the performance and speed-to-market advantages of programmable logic with a minimal software investment".
Warp R6.3 adds the ability to specify timing constraints for all of the Delta39K CPLDs and programmable PHY devices.
Significant run-time improvements have been made to the Warp front end in all versions of the Warp development tool to speed up the design process.
For Warp Professional and Enterprise versions, compilation time enhancements have been made to the design flow manager.
Cypress has also added valuable features such as report file bookmarking to improve project management and expanded support for Delta39K family of CPLDs.
On the PC platform, Warp R6.3 includes the post-synthesis timing simulator Active-HDL SIM version 3.3 and the finite-state machine (FSM) editor Active-HDL FSM, from Aldec.
Active-HDL Sim is a full-featured post-synthesis VHDL timing simulator that supports simulation of VHDL and Verilog files compiled to Cypress devices.
Cypress continues to offer a value-driven $99 edition of Warp R6.3, along with two editions that provide additional design functionality: Warp Professional and Warp Enterprise.
Cypress also offers industry-leading value by providing customers with free technical support and free upgrades for life.
The Warp R6.3 update is free to existing Warp tool users and can be downloaded off the Cypress website.
• Cypress Semiconductor: contact details and other news
• Other news in Design and Development Software
• Email this news to a colleague
•
• RSS news feed for Cypress Semiconductor
• RSS news feed for Design and Development Software
• Electronicstalk Home Page
Copyright © 2000-2006 Pro-Talk Ltd, UK. Based on news supplied by Cypress Semiconductor - Subject: Warp R6.3
Click on the advertisement to visit the advertiser's web site now