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Company news from CoWare
Date: 21 December 2004Company contact details

 
Electronic system-level design on show in India

CoWare will showcase its electronic system-level design solutions for the fast-growing embedded systems market at the VLSI Design 2005 and ICES Conference in India next month.

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CoWare will showcase its electronic system-level (ESL) design solutions for the fast-growing embedded systems market at the vlsi Design 2005 and ICES Conference - to be held in Kolkata, India, from 3rd to 5th January 2005.
At the conference - which combines the 18th International Conference on VLSI Design and the 4th International Conference on Embedded System - CoWare experts will offer insights into ESL technology and market trends through delivering the keynote address, technical papers, industry forum presentations, and product demonstrations.
'The international VLSI Design conference has a proud tradition of bringing together top researchers from academic institutions, research laboratories and high-technology companies worldwide, and this year is no exception, with all major industry players gathering for the 18th consecutive year', said Partha Pratim Das, General Co-chair, VLSI-18 and ICES-4, 2005, and Head of Engineering, Interra Systems.
'It is particularly encouraging to find new companies coming forward to support the conference'.
'We are quite excited to have CoWare, a leading supplier of ESL solutions, participate as a silver sponsor in the first year of the company's operations in India'.
'This will greatly help increase awareness of ESL technology and its influence in the fast growing embedded systems design market in India'.
Alan Naumann, CoWare's president and CEO, will deliver the conference keynote address, 'ESL - the next leadership opportunity for India'.
Naumann will discuss keys to success in the ESL market and how India can contribute to the growth of the market.
'In 2004, CoWare focused on driving adoption of ESL in India - including announcing the opening of CoWare India Private for R and D and system-level IP model library creation - because we believe India is becoming a pivotal player in the growing ESL market', said Naumann'.
'As more and more Indian companies focus on product design - not just software design - they are looking to ESL methodologies to help solve problems associated with increasing complexity and hardware-software codesign'.
'Because the VLSI Design 2005 and ICES Conference is uniquely dedicated to designers of both hardware and software systems, it is a perfect venue for Indian companies to hear about the latest developments and keys to success in this increasingly competitive market'.
In the CoWare booth, visitors can see demonstrations of CoWare's leading esl design tools, including SPW - the most comprehensive DSP application solution that bridges the gap from dsp algorithm exploration to implementation into hardware and software; as well as its ConvergenSC system-level design solution - featuring the industry's fastest SystemC simulator - and the Lisatek suite of tools for embedded processor modelling, design, and software tool generation.
CoWare application engineers will be available onsite to answer visitors' questions.
At the conference Industry Forum, representatives from various companies will discuss emerging technologies and major successes in the Indian market.
Representatives from Infineon Bangalore will present a paper titled 'Modelling of application specific instruction set processor and customisation of the tools generated', based on their success using CoWare's Lisatek products for ASIP design.
CoWare will also present a paper titled 'Embedded software development in the platform context', addressing challenges and solutions for software development on complex SoCs.
CoWare will also present two papers during the conference technical programme.
The first, jointly presented by CoWare and the Indian Institute of Technology (IIT) Delhi, is titled 'Extracting exact finite state machine from SystemC behavioural descriptions'.
The second, focused on embedded processor design, is titled 'A methodology and tooling enabling application specific processor design'.  

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