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CoWare has made a major expansion of its ConvergenSC Model Library with the addition of ARM PrimeCell peripherals.
The ConvergenSC Model Library, already the world's largest library of SystemC IP for embedded processor and on-chip bus designs, now contains critical IP platform models for peripherals.
Through co-operation with ARM, CoWare has used the golden RTL and test benches to create these SystemC PrimeCell models.
'Customers achieve significant time-to-market benefits by using the ARM PrimeCell peripherals in their soc designs', said Tim Mace, PrimeCell Product Manager, ARM.
'Having SystemC models of these PrimeCell peripherals available in esl design tools such as CoWare's ConvergenSC enables designers to easily analyse their system and software interactions and dependencies'.
'With ConvergenSC and the new SystemC ARM PrimeCell models, an SoC designer can quickly create advanced SoC architectures, analyse and optimise the architecture and perform hardware/software tradeoffs', said Mark Milligan, Vice President of Marketing, CoWare.
'We are continually adding important IP to the ConvergenSC Model Library to further speed the adoption of SystemC and ConvergenSC'.
Using these new additions to the ConvergenSC Model Library, customers can now analyse how these validated individual PrimeCell peripherals interact in a complex SoC.
ARM PrimeCell models that are included in the library are from the PrimeCell System Products, PrimeCell Ancillary Products, PrimeCell Memory Controllers and peripherals from the ARM PrimeXsys Platform.
Additional models will be added to the library based on customer demand.
SoC performance-critical peripherals, such as DMA controllers, memory controllers and other AHB components, are modeled and verified to be cycle accurate, ensuring that architects can validate hardware and software performance months before the design is implemented in RTL.
The new peripheral models have been in use at a major customer and are now available for additional beta customers.
Production release is scheduled for Q1 2005.
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