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SystemC-based processor support packages (PSPs) for the MIPS32 24K core family have been added to CoWare's extensive ConvergenSC Model Library.
Together with CoWare's ConvergenSC system-level design solution, the PSPs help MIPS Technologies' customers make price/performance tradeoffs and beat their performance goals for highly competitive, complex SoC designs by allowing them to explore and debug their designs at the system level.
The PSPs for the MIPS32 24K cores - the embedded industry's highest performance 32bit synthesisable processor cores - are the latest in a series of models developed through an ongoing partnership between the companies.
"These jointly developed PSPs - available through CoWare - have the speed and cycle accuracy of the latest version of the MIPSim instruction set simulator (ISS) combined with CoWare's powerful analysis capabilities, offering our mutual customers the best solution for their design needs", said Russ Bell, Vice President of Marketing at MIPS.
"The PSPs will allow our OEM customers to understand critical performance tradeoffs and the influence of Embedded software early in the design cycle".
"This is extremely important in markets for powerful, graphical, performance-driven applications such as digital and interactive television, set-top boxes and DVDs, where meeting performance goals is critical to remaining competitive".
"With the PSPs for the MIPS 24K cores, our mutual customers can now verify and modify SoC hardware and software performance before RTL, allowing them to increase performance, decrease costs and create embedded systems ideally tuned for their competitive applications", said Mark Milligan, Vice President of Marketing, CoWare.
The MIPS32 24K core family, which includes the 24Kc, 24Kc Pro, 24Kf and 24Kf Pro versions, offers performance from 400 to 550MHz worst case in a 0.13-micron process, the highest frequency available in 32bit synthesisable cores for embedded markets, while minimising design time and reducing product costs.
By running simulations in ConvergenSC - which speeds the concurrent design of SoCs with embedded software by combining hardware/software partitioning, platform assembly, simulation, debug and analysis capabilities - together with the CoWare PSPs, users can quickly determine the optimum architecture for their specific application and debug their software and hardware early in the design process.
The tools let customers perform detailed analysis of processor throughput and latency, as well as Memory subsystem performance and bus analysis.
Analysis results can be viewed graphically and used to determine how a design should be refined.
With the ability to measure the key parameters that affect the performance of the processor in their design, users can design better performing systems optimised around the MIPS32 24K cores.
The new PSPs are also integrated with the Debugger in CoWare's LisaTek product - a fully integrated solution for embedded processor modelling, design, and software tool generation.
This adds full embedded software debug capabilities such as source and assembly level debug, viewing and tracing memory and internal registers, and complete control of the core.
The new CoWare PSPs are compatible with the MIPS Software Toolkit, including the MIPS SDE software tool chain (compiler, assembler, and linker) for the processor.
The PSPs are cycle accurate, supporting MIPS features such as an eight-stage pipeline, configurable instruction and data cache, MMU configurable dual-entry joint TLB and OCP on-bus interconnect.
CoWare's PSPs for the MIPS32 24K core family will be available in production release in Q3 2004.
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