News Release from: Carbon Design Systems
Edited by the Electronicstalk Editorial Team on 24 September 2004
Acceleration for VHDL and mixed-language designs
Carbon Design Systems has added VHDL and mixed language (VHDL and Verilog) support to its product line.
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Carbon Design Systems has added VHDL and mixed language (VHDL and Verilog) support to its product line. Since debuting last year, Carbon's SpeedCompiler and DesignPlayer products have been used to greatly enhance Verilog runtime performance, on the order of 10-50x faster than popular simulators. New SpeedCompiler options now allow the same level of acceleration for VHDL and mixed-language designs.
"The addition of VHDL support to our product line enables us to address the needs of a global design market", proclaimed Steve Butler, President and CEO of Carbon.
"We are now strongly positioned to carry our worldwide expansion to the European market and build a strong foundation for success, as we have in North America and Asia".
"Supporting VHDL is an imperative for building a broad customer base in Europe and supporting our current customers that have mixed language requirements", noted Alan Swahn, Vice President of Marketing at Carbon.
"Our customers can now deploy a single executable model of their design, even though its constituent parts may be a combination of VHDL, Verilog, and C".
Carbon's SpeedCompiler software reads synthesisable Verilog and/or VHDL and generates a high-performance engine - DesignPlayer.
DesignPlayer can represent one or more chips and multiple engines can represent a system that encompasses hundreds of millions of gates.
DesignPlayer is a soft-model that is accurate to the hardware - cycle and register accurate.
DesignPlayers can run standalone, be linked into C, C++ test environments, or even be directly coupled to a SystemC simulator as a callable model.
DesignPlayer users have the performance they need to validate firmware, software drivers, and diagnostics, while maintaining the hardware's errata.
SpeedCompiler typically serves a large engineering project group working across an enterprise and is priced from $200,000-$350,000 for an annual subscription.
DesignPlayer engines for development are $10,000 per seat in volume and engines for IP deployment are under $2000 per seat in volume.
SpeedCompiler-Verilog has been used for over a year by Carbon's customers, including EMC, Sun Microsystems, and Agere Systems.
SpeedCompiler-VHDL is being tested by several customers today and is targeted for general availability by October of this year.
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