Product category: Design and Development Software
News Release from: Clear Shape Technologies
Edited by the Electronicstalk Editorial Team on 30 November 2006

DFM solutions come to market

Clear Shape Technologies has formally introduced itself as a design-for-manufacturing solutions provider

Clear Shape Technologies has formally introduced itself as a DFM solutions provider delivering variability solutions that enable chip designers to control and optimise the parametric and catastrophic impact of systematic manufacturing variations. After 3 years of development of key patent-pending technologies and successful joint work with several customers and foundries, Clear Shape has also announced two products that enable designers and manufacturers to achieve entitled performance and yield.

Clear Shape has raised $10 million of funding to date, from premiere firms such as USVP, Intel Capital, KT Ventures (KLA-Tencor) and AsiaTech.

The company's board of outside directors includes Winston S Fu, PhD, General Partner, US Venture Partners, and Professor Thomas Kailath, Hitachi America Professor of Engineering, Emeritus, Stanford University.

'The foundation that was the basis for the contract between IC design and manufacturing has been shaken as 'rule-based' assumptions have steadily crumbled'.

'Manufacturing variations now dramatically and adversely impact chip performance and yield'.

'There is a dire need for tools and technologies that reinstate designers' confidence that their chips will achieve entitled performance and be manufacturable at high yields', stated Atul Sharan, President and CEO of Clear Shape.

'For three years now, Clear Shape has been focused on building innovative model-based solutions from the ground up resulting in its Variability Platform'.

At 90nm and below, systematic variations are the greatest cause of catastrophic chip failures and electrical issues related to timing, signal integrity and leakage power.

For example, at 65nm, systematic variations of 3nm on a transistor gate can cause a 20% variation in delay and have a 2x impact on leakage power.

Up to 90nm, the industry addressed 'yield' issues with post-tape-out compute-intensive OPC and RET techniques without designers getting involved.

This landscape changes at sub90nm when systematic variations affect both designers and manufacturers.

These pattern-dependent systematic variations due to lithography, CMP etc cannot be accounted for using traditional rule-based tools and methodologies.

With the current corner-based design methodologies and tools, margins are applied everywhere regardless of context.

This over-design with excessive guard-banding can result in chip performance that is dramatically lower than entitled performance, also resulting in unexpected parametric and catastrophic failures.

To address these fundamental limitations of the current design infrastructure, Clear Shape has developed a variability platform based on its innovative model-based solution that incorporates process information related to lithography, RET, OPC, CMP, mask, etch, interconnect parasitics and transistor modelling.

Instead of working from ideal layout and approximating the systematic variations effects through excessive rules and margins, designers can now implement, verify and optimise their design based on true silicon shapes, quickly and accurately detect potential manufacturing failures during physical design and use Clear Shape's in-context model-based electrical DFM to optimise their electrical parameters within their existing rule-based design tools.

Clear Shape's goal is to enable designers to achieve entitled performance and yield by providing tools and technologies that fit nondisruptively into existing design flows.

Dr Yao-Ting Wang, cofounder, CTO and Chairman, was a cofounder of Numerical Technologies, where he drove development of technology and products that address fundamental problems that resulted from ever-decreasing feature sises falling below the wavelength of light source used in the lithography systems.

He has extensive technology expertise in the fields of lithography, lithography simulation, and its impact on the EDA design flow, and is the inventor of some key RET techniques that are in wide use.

Atul Sharan, cofounder, President and CEO, was resident at Mohr-Davidow ventures, a premier Silicon Valley venture capital firm, prior to cofounding Clear Shape.

Earlier, as Vice-President, he led Synopsys's DFM strategy following their acquisition of Numerical Technologies, where he had served as Senior Vice President of Sales and Marketing.

Sharan also held executive positions at Ambit and VLSI Technologies/Compass.

Dr Fang-Cheng Chang, cofounder, VP of Engineering, was a founding employee of Numerical Technologies, and as VP of R and D he led all the early development efforts that spanned the company's entire product lines from design to manufacturing and was a substantial contributor to the company's patent portfolio.

Other members of Clear Shape's executive team include: Dr Nishath Verghese, VP of Engineering for Design Technology, who led engineering for Cadence's timing library characterisation, delay calculation products, and noise analysis core engines, and was an architect and principal at CadMOS Design Technology.

Nitin Deo, VP of Marketing, Business Development and International Sales, worked as Sr VP of Marketing and Business Development at Ponte, and as GM for Japan operations and VP of marketing and business development at Magma.

Deo has also worked at Synopsys, Fujitsu and Philips.

Dr Philippe Hurat, Sr Director of Customer Applications and Technical Marketing, has over 15 years of experience in the semiconductor and EDA industries spanning chip-design, product management and applications.

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