Upgrade for programmable logic design suite

The latest version of Celoxica's DK1 Handel-C-to-hardware design suite includes new features for system-level hardware and software codesign.

The latest version of Celoxica's DK1 Handel-C-to-hardware design suite includes new features for system-level hardware and software codesign, cosimulation support for ARM and PowerPC embedded processors, improved synthesis, enhanced area and delay analysis, improved VHDL output, Verilog output, 100 times faster simulation, and support for Actel, Altera Excalibur and Xilinx Virtex II Pro devices.

The DK1.1 design suite supports the design, validation, iterative refinement and implementation of complex algorithms in hardware.

It includes built-in design entry, simulation, and synthesis - all driven by Handel-C.

Handel-C is based on ANSI-C extended with concepts for timing, concurrency, flexible-width variables and resource allocation to let software engineers and hardware designers quickly implement complex algorithms efficiently in hardware.

"With the launch of DK1.1 and introduction of PAL and DSM technologies, Xilinx's relationship with Celoxica is returning real value to its customers", said Rich Sevcik, senior vice president of the FPGA Products Group at Xilinx.

"The simplicity of Handel-C, PAL and DSM make it