News Release from: Concept Engineering
Edited by the Electronicstalk Editorial Team on 15 April 2005

Fragmented approach aids transistor-level debug

New software improves transistor-level debugging and optimisation for IC and SoC designers using the Virtuoso Schematic Editor environment from Cadence Design Systems.

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Concept Engineering has developed a product that improves transistor-level debugging and optimisation for IC and SoC designers using the Virtuoso Schematic Editor environment from Cadence Design Systems. The new product, which Concept Engineering developed as a member of the Cadence Connections programme, is an option to Concept's SpiceVision Pro that automatically generates schematic fragments - critical paths or sections of a circuit - and exports them into the Cadence Virtuoso Schematic Editor environment. The product is based on 'Skill', a language developed by Cadence that enables users to customise the Cadence technology and create interfaces with external tools that work with the Cadence environment.

Once schematic fragments are imported into the Cadence environment, designers can use the schematic fragments to perform transistor-level debugging and optimisation.

Surrounding circuit structures do not affect the schematic fragments during debugging, so simulation takes less time to complete.

SpiceVision Pro automatically creates easy-to-read circuit schematics from both pre- and post-layout transistor-level structures (Spice netlist descriptions).

A schematic interface to the Cadence environment using Skill enables mutual customers to easily process design data.

For example, designers can now easily simulate a critical path at the transistor level.

The path is created by means of SpiceVision Pro and is exported into the Cadence Virtuoso Schematic Editor environment.

'Nanometre technology is forcing design engineers to understand, optimise and debug their chip designs at the transistor-level', said Gerhard Angst, President and CEO of Concept Engineering.

'SpiceVision Pro and the new Skill interface help with this process'.

Azul Systems, pioneer of the industry's first network attached processing solution that promises to dramatically alter economics around the delivery of compute resources, has built an innovative multicore processor-chip technology using SpiceVision Pro and the Skill interface.

This technology finds circuit fragments that need to be taken back into the Cadence software for further analysis and debugging.

'The ability of the new interface to 'cookie cut' schematic fragments saves us from analysing and debugging a full circuit description', said Scott Sellers, Azul System's Vice President of Hardware Engineering, CTO and cofounder.

'Therefore, we're now saving substantial simulation time'.

'The Cadence Connections programme promotes collaboration and helps bring emerging third-party solutions to the customer's design chain quickly', said Pat Dutrow, Director of the Cadence Connections programme.

'Our users wanted an efficient flow for transistor-level debugging'.

'Concept Engineering has a complementary debug solution that, when combined with the Virtuoso environment, helps address specific customer needs such as post-layout transistor-level debugging and circuit fragment simulation'.

'This is a good example of how Cadence uses an open collaboration approach to deliver customer-focused solutions'.

The Skill-based schematic fragment export capability is available immediately as an option to SpiceVision Pro.

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