Product category: Intellectual Property Cores
News Release from: Cambridge Consultants | Subject: XAP4
Edited by the Electronicstalk Editorial Team on 2 December 2005
16bit core performs
more MIPS per megahertz
The all-new 16bit XAP4 IP core features a modern, high-performance RISC architecture with low gate count, low power consumption and high code density
Cambridge Consultants has released a new 16bit RISC microprocessor IP core, which it will feature at the Design and Reuse IP-SoC conference in Grenoble, France on December 7th and 8th 2005. The all-new 16bit XAP4 features a modern, high-performance RISC architecture with low gate count, low power consumption and high code density.
This article was originally published on Electronicstalk on 2 December 2005 at 8.00am (UK)
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It is optimised for use in cost and performance sensitive ASIC designs and is available for evaluation now.
On a 0.18um CMOS fabrication process, the XAP4 can deliver up to 63DMIPS at a clock frequency of 117MHz.
This benchmark performance of 0.54MIPS/MHz is a 50% improvement over Cambridge Consultants' previous 16bit processor, XAP2, which has been manufactured in hundreds of millions by licensees such as CSR, and in ZigBee radios, automotive devices and low-power industrial and medical sensors.
The XAP4 has both 16bit data and address buses and is capable of running programs up to 64Kbyte.
The first implementation of the processor has a two-stage pipelined Von Neumann architecture.
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It is delivered to licensees as a soft IP core in Verilog RTL that can be synthesised in as few as 12,000 gates for ASICs where die size and power consumption must be as small as possible.
Cambridge Consultants has already delivered XAP4 to one licensee and is in discussion with other prospective customers at present.
'This latest core fills a large gap in the market for ASIC processors', says Alistair Morfey, a Technology Director at Cambridge Consultants.
'Many ASIC designs require good computing performance combined with low power and low cost'.
'This is best met by a processor with high code density, which minimises the cost and power of the program memory in ROM or Flash'.
'Some 32bit cores offer similar code density when run in their 16bit mode, but designers are still paying for a 32bit wide core and RAM inside their ASIC, which will cost twice as much in silicon as a 16bit system'.
'Every push and pop consumes extra power by doing 32bit RAM accesses instead of 16bit'.
'In fact, there are probably hundreds of ASIC designs out there using more expensive 32bit processor cores, when an advanced 16bit core would do just as well', continues Morfey.
'A 16bit databus offers adequate precision for most applications, and the XAP4 program size of 64Kbyte caters for a wide variety of real-world applications'.
The 16bit XAP4 is the latest addition to Cambridge Consultants' microprocessor core lineup.
There is also the 32bit XAP3 for more demanding applications, and in development is the XAP5 that also uses 16bit data but extends the address bus to 24bit, providing support for larger program sizes up to 16Mbyte.
All these processor cores include Cambridge Consultants' SIF debug logic, which provides full control over the processor and access to its debug registers, together with noninvasive access to any part of the processor's memory map for data acquisition while a system is running.
The architecture and design of the XAP3, XAP4 and XAP5 processors was conceived at Cambridge Consultants to fulfil the requirements of modern ASIC-based systems running code written by different programmers including real-time operating systems.
All the processors include hardware support for privileged operating system modes where code running in user mode cannot corrupt supervisor or interrupt code.
Code is position independent and there is also support for unaligned data access, making programs easy to port and quick to run.
Most programs will be written in C and the processors feature direct support for many of the language constructs, which results in higher code density.
There is hardware support for rapid context switching, for example, when interrupts occur, and there are multi-cycle instructions to speed up multiply, divide and block copy operations.
All of Cambridge Consultants' XAP microprocessors are supported by its xIDE integrated software development and debug environment, which includes a programmer's editor, assembler, debug interface, instruction set simulator, project build manager and GCC compiler, which provides the path for programming in C++.
xIDE is quick and easy to install and use on Windows PCs, with Linux/Unix and Mac OS versions also available.
xIDE can be customised to add features specific to a licensee's ASIC or ASSP, and licensees can brand and deliver xIDE to their developers.
Other advanced technical features of the XAP3, XAP4 and XAP5 include: hardware support for operation as a slave processor when a master processor downloads a code image and bootstraps the XAP, support for multiprocessor debug over SIF and architectures for combining XAP with Cambridge Consultants' APE signal processing engine, which offers a dynamic datapath routing capability.
Chris Turner, Business Development Manager at Cambridge Consultants, said: 'Licensees like the way XAP cores are delivered in Verilog RTL complete with software and debug tools'.
'This user-friendly delivery format combined with our high level of customer support, including access to the XAP design team, means ASIC designers can apply XAP cores with confidence'.
Turner also commented: 'Cambridge Consultants' royalty-free business model also means that semiconductor companies adopting XAP processors can simplify their business and gain a significant increase in profitability over the production lifetimes of a range of products'.
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