Reference design targets UMC 65nm process

Cadence Design Systems and UMC's reference flow enables customers to achieve optimal 65nm low-power designs when used with UMC's Low Power Kit.

Cadence Design Systems and UMC have released a common power format (CPF)-based, low-power reference design flow targeted to the UMC 65nm process.

This reference flow enables customers to achieve optimal 65nm low-power designs when used with UMC's Low Power Kit, which includes CPF-enabled libraries and other intellectual property.

This 65nm low-power reference design flow uses UMC's Leon test chip as the reference design.

Leon is an open source 32bit RISC microprocessor core with other complex elements including SRAM.

The Leon chip was partitioned into multiple voltage domains using the Cadence Low-Power Solution for design, verification, implementation and analysis.

The combination of the 65nm reference design flow and the UMC Low Power Kit enables increased productivity while managing design complexity, shortening time to market and reducing manufacturing risk.

The UMC 65nm low-power reference design flow highlights key capabilities of the Cadence Low-Power Solution, including the Cadence Incisive Unified Simulator for gate-level low-power simulation; the Cadence Encounter RTL Compiler for synthesis, low-power and DFT cell insertion; and the Encounter Conformal Low Power for equivalence checking and low power design implementation checking.

The system also includes the Encounter Test for ATPG; the SoC Encounter RTL-to-GDSII system for floorplanning, powerplan and place-and-route; the Encounter Timing System for timing and SI signoff; the Cadence QRC Extraction; the VoltageStorm PE for static power and IR analysis; and the VoltageStorm DG and Virtuoso UltraSim for dynamic analysis of current surge at power up.

In addition, UMC's Low Power Kit, including its CPF-enabled library, was validated as part of the reference design flow development.

"We are working closely with Cadence to address complex design issues that face designers at 65nm, while enabling faster time to volume through an integrated low-power solution", said Darsun Tsien, UMC's Vice President of design methodology.

"Through our ongoing collaboration with Cadence, we are able to provide designers with validated low-power technologies to manage power concerns and meet aggressive time to market goals".

"This CPF-based flow, the result of a joint effort between Cadence and UMC, accelerates implementation of low-power designs", said Chi-Ping Hsu, Corporate Vice President of IC Digital and Power Forward at Cadence.

"The combination of UMC process technology and the Cadence Low-Power Solution provides our mutual customers with the ability to realise their aggressive project goals while preserving low-power intent throughout the design process".

This reference flow package includes design resources, implementation scripts, an application note and a comprehensive workbook.

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