Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial Team on 26 September 2007
Statistics prevent catastrophic silicon
failures
Advanced statistical timing analysis and optimisation technology allows Renesas to accurately account for the effects of process variability in its leading-edge 45nm digital designs.
Renesas Technology Corp has adopted statistical static timing analysis (SSTA) technology from the Cadence Encounter digital IC design platform as part of its next-generation design flow This advanced statistical timing analysis and optimisation technology - an integral part of the Cadence Encounter Timing System and SoC Encounter RTL-to-GDSII System - allows Renesas to accurately account for the effects of process variability in its leading-edge 45nm digital designs
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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