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Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Virtuoso UltraSim
Edited by the Electronicstalk Editorial Team on 07 February 2006
Simulator speeds to FastSpice results
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Sirific Wireless has successfully designed its single-chip CMOS RF transceiver for HSDPA/W-Edge using the Cadence Virtuoso UltraSim full-chip simulator for FastSpice simulation.
Fabless RF semiconductor company Sirific Wireless has successfully designed its single-chip CMOS RF transceiver for HSDPA/W-Edge using the Cadence Virtuoso UltraSim full-chip simulator for FastSpice simulation The Virtuoso UltraSim simulator enabled Sirific to cut its verification time from two weeks to eight hours, allowing development in record time while ensuring silicon accuracy critical for mixed-signal designs