Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Chip Optimiser
Edited by the Electronicstalk Editorial Team on 31 January 2006
Software optimises IC designs in 3D
Cadence Chip Optimiser is an innovative silicon-proven full-chip optimisation system
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Cadence Design Systems has released its new groundbreaking manufacturing-aware chip optimisation product Cadence Chip Optimiser, an innovative silicon-proven full-chip optimisation system. Cadence Chip Optimiser is used after conventional place and route and before design tape out to improve the yield, manufacturability and performance of complex IC designs.
Cadence developed Chip Optimiser as part of its growing family of world-class manufacturing and yield-aware offerings aimed at addressing the industry's most pressing design for manufacturing (DFM) and design for yield (DFY) challenges.
Conventional IC implementation tools create an oversimplified model of interconnect and foundry manufacturing process rules.
Cadence Chip Optimiser uses a three-dimensional space-based optimisation approach which models, analyses and optimises true shapes and intervening physical spaces.
This provides a more accurate and realistic 'map' of the design, and clearly indicates where important optimisations may be made.
Shapes and spaces can be positioned in the exact configuration and location required to correct for subwavelength, spacing and topological effects.
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This approach enables greater precision and flexibility in optimisation.
'Cadence and ATI have worked together for more than 3 years to bring a critical set of manufacturing optimisations into the design phase', said Greg Buchner, Vice President of Engineering at ATI.
'We have used the Cadence Chip Optimiser technology on more than 10 tapeouts at multiple foundries, including the graphics processor for the Microsoft Xbox 360 and the world's fastest consumer PC graphics processor, our recently announced Radeon X1900 XTX'.
'Cadence Chip Optimiser plays a vital and ever-growing role in helping ATI achieve our design, manufacturability and yield goals'.
This technology performs interconnect topology optimisations, while taking into consideration manufacturing and electrical constraints on digital or custom designs.
'Cadence Chip Optimiser has performed flawlessly on our 65nm microprocessor design methodology', said Mark Papermaster, Vice President of Microprocessor and Systems Technology Development at IBM Corp.
'The truly collaborative partnership we have with the Cadence Chip Optimiser team for the last 3.5 years has been an ideal working relationship'.
'The extensive time we spent together understanding and addressing the design for yield and manufacturing challenges was key'.
'We achieved closure to our design goals on schedule, in an automated and predictable manner'.
Cadence Chip Optimiser is built on innovative technology developed in Cadence's Project Catena technology incubator and can be applied to a broad range of design styles and process nodes.
This is demonstrated by tapeouts and production silicon for high-volume designs at leading-edge process nodes for markets including high-end consumer, graphics processors and microprocessors.
'Unlike many contemporary technology developments purporting to solve manufacturability issues at advanced process nodes, this product represents a fundamental breakthrough in chip scale physical and electrical modelling', said Ted Vucurevich, CTO of Advanced Research and Development at Cadence.
'Integrated with incremental signoff quality analysis and advanced optimisation capability, this technology allows us to accurately handle today's most demanding subwavelength lithography and manufacturing process rules, and sets the stage to efficiently evolve our capabilities in accordance with the currently published International Semiconductor Association roadmap'.
Cadence Chip Optimiser works seamlessly with the Cadence Encounter digital IC design platform and the Virtuoso custom design platform.
It is a native application on the OpenAccess database.
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