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Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter GXL
Edited by the Electronicstalk Editorial Team on 25 January 2006
65nm design flow maximises platform
benefits
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Fujitsu has adopted the Cadence Encounter digital IC design platform in its new internal reference design flow targeted at 65nm chips.
Fujitsu has adopted the Cadence Encounter digital IC design platform, with Encounter RTL Compiler GXL and SoC Encounter GXL technology, in its new internal reference design flow targeted at 65nm chips The Encounter-based flow has, to date, produced 150 high-end production ASICs at or below 130nm with all first silicon success, out of which about 30 designs were developed at 90nm
This article was originally published on Electronicstalk on 6 Dec 2005