Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 29 November 2005
Encounter Test family
validated on Agilent's 93000
The Cadence Encounter Test family of products has been validated on Agilent's 93000 SOC Series automated test system
With this validated test and diagnostic flow between electronic design automation (EDA) and automated test equipment (ATE), joint customers can be confident of higher-quality tests, faster test program creation, and more rapid resolution of yield limiters for their most challenging nanometre designs.
This article was originally published on Electronicstalk on 29 November 2005 at 8.00am (UK)
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The validation of the test and diagnostics flow enables interoperability through industry-standard formats including Standard Test Interface Language (STIL) and Waveform Generation Language (WGL).
This interoperability is critical for a smooth hand-off between the Encounter True-Time Delay Test and Agilent 93000 users and for shortening the time to fully operational production test.
'As a result of our work with Cadence on this important project, our joint customers will have confidence in their test and yield diagnostics flow when they use Encounter Test on the Agilent 93000', said Pascal Ronde, Vice President of Agilent's Semiconductor Test Solutions.
'This linking of EDA and ATE for test generation and diagnostics removes a significant barrier to meeting critical time-to-market requirements faced by semiconductor companies without such a validated flow'.
The collaboration also validated Encounter Diagnostics, which identifies critical design-related issues by analysing failure data from automated test systems to identify sources of yield loss.
This requires full compatibility with the tester to assure that tester failure data efficiently interfaces to Encounter Diagnostics' Chip Pad Pattern (CPP) format.
'This level of interoperability between test generation, ATE and diagnostics will speed our customers' test development time, improve product quality, and shorten yield ramp times', said Sanjiv Taneja, Vice President of R and D for Encounter Test, at Cadence.
'The efforts of Cadence and Agilent demonstrate both companies' commitment to address our customers' needs through a tight collaboration'.
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