Cadence commits to e standardisation: News from Cadence Design Systems

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Responding to user demand for a proven standard verification language, Cadence Design Systems has stepped up its support for the IEEE P1647 e standardisation effort. Cadence has contributed resources for technical editing and program management to ensure the standard is of the highest quality and completed on time. The Cadence contribution comes as increased participation and interest in the IEEE working group has enabled a dramatic compression in the schedule for completion.

The technical content of the standard was completed on 6th June 2005 four months ahead of schedule.

The e language is an extremely powerful and mature system-level verification language that is in use today by an overwhelming majority of industry leaders in consumer electronics, telecommunications, semiconductors and IP.

By standardising the language within IEEE and opening it up to development, customers will benefit as market-leading products such as Specman Elite, which has been used to verify thousands of designs, are joined by a burgeoning marketplace of e-based tools.

These complementary technologies will also be accelerated to market by the openness and stability provided by an IEEE-backed standard.

'LSI Logic has proven expertise in e and advanced verification methodologies on complex IP blocks and entire systems'.

'We have a significant interest in the standardisation of e and participated in the drive toward e standardisation by joining the LicenseE programme in 2002', said Jeff Vanderlip, Director of ASIC Marketing at LSI Logic.

'LSI Logic applauds Cadence's increased support for the IEEE P1647 e standardisation effort, and would like to see standardisation of the e language so that it is open and available to everyone'.

'ARM is fully supportive of the IEEE P1647 e standardisation effort and standards in general', said John Goodenough, Director, Design Technology, ARM.

'e has been an integral part of our verification methodology, and it is good to see it move closer to standardisation'.

'We expect that this process will encourage the proliferation of competitive tools based on the e language and will be extremely positive for our partners since it ensures the stability of e and provides them with a choice of tools'.

Because of the complexities of today's designs, specialisation of engineering functions is becoming the rule rather than the exception.

This move to specialisation emphasises the fact that no single language addresses everyone's needs in the verification cycle.

For example e has become the language of choice for verification specialists, SystemVerilog serves design teams who need incremental verification power and SystemC has become the language of choice for system architects.

'Silicon Image's leadership in high-speed serial communications cores depends on our IP working smoothly in our customers' mixed-language design and verification flow, and we see e playing a very important role', said Eric Almgren, Vice President of Business Development and IP Licensing of Silicon Image 'From the verification of our cores and delivery of verification IP in e to the incredibly complex systems our customers develop, there is no way you'll get your design out the door on schedule without supporting the preferred language each specialist requires in the design chain'.

With its Incisive verification platform, Cadence offers the only multilanguage verification technology.

The company's all-inclusive position on verification languages benefits customers by allowing each specialist an optimal blend of e, SystemC and SystemVerilog languages.

As the industry continues to drive standards, each language will emerge and find its optimal place in the verification landscape based on its strengths - similar to incumbent HDLs like Verilog and VHDL.

'Novas' market-leading debug systems offer multilanguage support to align with the needs of the full range of specialists in the design and verification flow'.

'We have supported the e verification language for several years to serve the needs of our customers using advanced verification process automation', said Scott Sandler, CEO, of Novas.

'We fully support open standards; faster standardisation of e will benefit our customers and the language itself'.

'With project and process level automation becoming more and more critical, Cadence has come to the realisation that the best way to support customers is to offer support for standards that address the needs of each specialist in the verification process', said Victor Berman, Director of Language Standards at Cadence.

'We don't subscribe to the approach that dictates to users the language they must use for a given task'.

'The bottom line is we support choice'.

The IEEE initiated a ballot on the e LRM on 27th September 2005.

If the ballot passes, the e functional verification language is expected to be standardised by the IEEE by March 2006.

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News Release from: Cadence Design Systems Edited by the Electronicstalk Editorial Team on 18 October 2005

Cadence commits to e standardisation

Cadence Design Systems has stepped up its support for the IEEE P1647 e standardisation effort.

Note: Readers of the Editor’s free email newsletter will have read this news when it was announced. . It’s free!

News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 18 October 2005