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Product category: Design and Development Hardware
News Release from: Cadence Design Systems | Subject: Palladium II
Edited by the Electronicstalk Editorial Team on 16 February 2005

Emulation system speeds
DTV chip verification

ATI Technologies has adopted the new Cadence Palladium II acceleration/emulation system to significantly accelerate the functional verification of its high-performance digital TV chip designs

ATI Technologies has adopted the new Cadence Palladium II acceleration/emulation system to significantly accelerate the functional verification of its high-performance digital television (DTV) chip designs. The Palladium II system, an integral part of the Cadence Incisive functional verification platform, was selected because of its ability to help accelerate the functional verification of the large, complex designs ATI uses to build chips used in high-end digital television sets.

'We needed to accelerate our verification to continue building the world's most advanced DTV chips', said David DiOrio, Vice President of Engineering, ATI Technologies.

'We chose the Cadence Palladium II system for our emulation and acceleration methodology because it was the best tool available from any vendor that delivered the required performance and flexibility that was promised'.

'The Palladium II system provided a single state-of-the art emulation and acceleration verification platform scalable from IP core development to full system-on-chip designs'.

The Palladium II acceleration/emulation system is built with advanced sub-100nm silicon, and leverages high-speed on-chip memory, high-bandwidth interconnect, and multi-chip-module packaging technology.

It delivers up to twice the speed and capacity of the first-generation Palladium system.

Built on the company's innovative processor-based verification technology, the Palladium II system is targeted at designers verifying the most complex system-on-chips in the wireless, networking, computing and multimedia markets.

The Palladium II system achieves an industry-first by reaching 256-million-gate capacity and is just one-third the size of the first-generation system.

'We continue to deploy our Palladium II systems successfully in the market', said Christopher Tice, Senior Vice President and General Manager, Verification Acceleration, Cadence.

'With more than 600 million gates of Palladium II installed worldwide, ATI has joined the growing list of customers that are satisfied with our Palladium systems and have decided to move up to our next-generation Palladium II system so they can increase their verification throughput'.

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